Methods of fabricating capacitor
AssigneeDongbu Electronics Co., Ltd.
InventorYoo Seon Song
Life of this patent
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Abstract
A fabricating method of a capacitor is disclosed. Particularly, a fabricating method of a capacitor which forms a capacitor in the place where the insulation layer of an STI region is removed, preventing interlayer dielectric layers from becoming thick. A disclosed method comprises: defining an STI region in the predetermined region of a substrate; removing the insulation layer of the STI region where a capacitor will be formed; forming a gate insulation layer and a first polysilicon layer on the substrate, and patterning the first polysilicon layer; and forming a first insulation layer and a second polysilicon layer on the substrate, and patterning the first insulation layer and the second polysilicon layer.
Claims19
A capacitor, comprising:
- a conductive well below an STI region in a substrate, the conductive well forming a bottom capacitor electrode;
- a first capacitor insulation layer in the STI region;
- an intermediate capacitor electrode on the first capacitor insulation layer having a side surface not in contact with the first capacitor insulation layer;
- a second capacitor insulation layer on the intermediate capacitor electrode;
- an upper capacitor electrode on the second capacitor insulation layer;
- and
- a third insulator layer having first, second and third vias respectively communicating with the conductive well and the intermediate and upper capacitor electrodes, wherein the first via directly communicates with the conductive well.
A capacitor, comprising:
- a conductive well below an STI region in a substrate, the conductive well forming a bottom capacitor electrode;
- a first capacitor insulation layer in the STI region;
- an intermediate capacitor electrode on the first capacitor insulation layer;
- a second capacitor insulation layer on the intermediate capacitor electrode, the second capacitor insulation layer having an area smaller than the first capacitor electrode;
- an upper capacitor electrode on the second capacitor insulation layer;
- and
- a third insulator layer having first, second and third vias respectively communicating with the conductive well and the intermediate and upper capacitor electrodes, wherein the first via directly communicates with the conductive well.
Dependencies are inferred from the claim text.