Thin film translator array panel and a method for manufacturing the panel
AssigneeSamsung Electronics Co., Ltd.
InventorsMun-Pyo Hong, Nam-Seok Roh, Hee-Hwan Choe, Keun-Kyu Song
Life of this patent
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Abstract
A gate wire including a gate line and a gate electrode is formed on a substrate and a gate insulating layer is formed on the substrate. A semiconductor pattern and an etching assistant pattern are formed on the gate insulating layer and a source/drain conductor pattern and an etching assistant layer are formed on the semiconductor pattern and the etching assistant pattern. A data wire including a data line and source and drain electrodes separated from each other is formed by removing the etching assistant layer and partly removing the source/drain conductor pattern. A pixel electrode connected to the drain electrodes is formed.
Claims7
A thin film transistor array panel comprising:
- an insulating substrate;
- a gate wire formed on the substrate and including a plurality of gate lines and a plurality of gate electrodes connected to the gate lines;
- a gate insulating layer formed on the gate line;
- a semiconductor layer formed on the gate insulating layer;
- a data wire formed on the semiconductor layer and including a plurality of data lines intersecting the gate lines, a plurality of source electrodes connected to the data lines, and a plurality of drain electrodes located opposite the source electrodes with respect to the gate electrodes;
- a plurality of pixel electrodes connected to the drain electrodes;
- and
- an etching assistant pattern made of the same layer as the semiconductor layer and located out of an area enclosed by the gate lines and the data lines.
Dependencies are inferred from the claim text.