Semiconductor device, method of manufacturing the same, sense amplifier and method of forming the same

A semiconductor device comprising:

• a first active region and a second active region in a substrate;
• a plurality of first unit circuits in the first active region, wherein each of the plurality of first unit circuits includes a plurality of first transistors, wherein each of the first transistors includes a first gate structure;
• a plurality of second unit circuits in the second active region, wherein each of the plurality of second unit circuits includes a plurality of second transistors, wherein each of the second transistors includes a second gate structure;
• a third transistor in the first active region, wherein the plurality of first unit circuits are electrically isolated from each other by the third transistor;
• a fourth transistor in the second active region, wherein the plurality of second unit circuits are electrically isolated from each other by the fourth transistor;
• a first insulation layer over the first, second, third and fourth transistors;
• a plurality of first plugs in the insulation layer, wherein the plurality of first plugs include a first gate plug electrically connected to the first gate structure of one of the plurality of first transistors, and a second gate plug electrically connected to the second gate structure of one of the plurality of second transistors;
• a plurality of second plugs in the insulation layer, wherein the plurality of second plugs include a first source plug and a first drain plug electrically connected to a first source region and a first drain region of the one of the plurality of first transistors, and a second source plug and a second drain plug electrically connected to a second source region and a second drain region of the one of the plurality of second transistors;
• a bit line and a bit line bar on the first insulation layer, wherein the first gate plug, the second gate plug, the first source plug, and the second source plug are electrically connected to the bit line or the bit line bar;
• a second insulation layer over the bit line and the bit line bar;
• a third drain plug electrically connected to the first drain plug or the second drain plug;
• and
• a wiring electrically connected to the third drain plug,
• wherein contact areas of the plurality of second plugs are substantially the same even if misalignments of the plurality of second plugs occur, so that contact resistances of the plurality of second plugs are substantially the same, and
• wherein the bit line is electrically connected to the first gate plug and the second source plug and the bit line bar is electrically connected to the second gate plug and the first source plug.