Dual metal integration scheme based on full silicidation of the gate electrode

A method of forming a semiconductor structure including fully silicide gates comprising:

• providing a Si layer on a surface of a gate dielectric layer that is located on a semiconductor substrate having at least one pFET device region and at least one nFET device region, said providing said Si layer comprises depositing a blanket layer of silicon atop the gate dielectric layer in both of the device regions, forming a patterned hard mask atop the Si layer in the nFET device region thereby protecting the Si layer in that region from a subsequent etching process, and thinning the exposed Si layer in the pFET device region by etching, and said Si layer atop said at least one pFET device region has a first thickness and said Si layer atop said at least one nFET device region has a second thickness, said first thickness is less than said second thickness;
• forming a Ge-containing layer comprising a polycrystalline SiGe alloy having up to 99.99 atomic % Ge by epitaxy on said Si layer in both device regions;
• forming a least one patterned gate stack in said pFET device region and forming at least one patterned gate stack in said nFET device region, each patterned gate stack comprises, from bottom to top, the gate dielectric layer, the Si layer and the Ge-containing layer;
• forming source/drain regions in said semiconductor substrate using each of said patterned gate stacks as an implant mask;
• selectively removing the Ge-containing layer of each patterned gate stack by etching thereby exposing said Si layer;
• implanting Ge atoms into the exposed Si layer within the pFET device region;
• implanting n-type dopants into the exposed Si layer within the nFET device region;
• and
• performing a silicidation process that hilly converts said Si layer within each device region into a silicide gate electrode, while simultaneously forming silicided source/drain regions, wherein said silicide gate electrode in said pFET device region has a height that is less than a height of the silicide gate electrode in the nFET device region, and the silicide gate electrode in said pFET device region comprises a metal rich silicide phase, while the silicide gate electrode in said nFET device region comprises a silicon rich silicide phase.