Field effect transistors and methods for fabricating the same
AssigneeAdvanced Micro Devices, Inc.
InventorsIgor Peidous, Patrick Press, Rolf Stephan
Life of this patent
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Abstract
Field effect transistors and methods for fabricating field effect transistors are provided. A method, in accordance with an exemplary embodiment of the invention, comprises forming a polycrystalline silicon gate electrode overlying a silicon substrate. The gate electrode has two parallel sidewalls. Two sidewall spacers are fabricated overlying the silicon substrate. Each of the two sidewall spacers has a sidewall that is adjacent to one of the two parallel sidewalls of the gate electrode. A portion of the gate electrode between the two sidewall spacers is removed.
Claims17
A method for fabricating a field effect transistor, the method comprising the steps of:
- forming a gate insulator overlying a silicon substrate;
- forming a polycrystalline silicon gate electrode in physical contact with the gate insulator, wherein the gate electrode has two parallel sidewalls;
- fabricating two sidewall spacers overlying the silicon substrate after the step of forming the polycrystalline silicon gate electrode, wherein each of the two sidewall spacers has a sidewall that is adjacent to one of the two parallel sidewalls of the gate electrode;
- removing a first portion of the gate electrode between the two sidewall spacers such that a second portion of the gate electrode remains between the two sidewall spacers;
- and
- forming metal silicide using the second portion of the gate electrode to form the metal silicide, the step of forming metal silicide performed after the step of removing a first portion of the gate electrode.
A method for fabricating a field effect transistor, the method comprising the steps of:
- depositing and patterning a layer of polycrystalline silicon overlying a silicon substrate to form a gate electrode, the gate electrode having sidewalls and defining a channel in the silicon substrate underlying the gate electrode;
- implanting first ions of a conductivity-determining impurity into the silicon substrate using the gate electrode as an implantation mask to form spaced-apart impurity-doped extensions;
- depositing a layer of spacer-forming material overlying the gate electrode;
- anisotropically etching the layer of spacer-forming material to form sidewall spacers disposed adjacent to the sidewalls of the gate electrode;
- implanting second ions of a conductivity-determining impurity into the silicon substrate using the gate electrode and the sidewall spacers as an implantation mask to form spaced-apart impurity-doped regions;
- removing a first portion of the gate electrode from between the sidewall spacers such that a second portion of the gate electrode remains between the sidewall spacers;
- and
- forming metal silicide using the second portion of the gate electrode and the spaced-apart impurity doped regions to form the metal silicide.
Dependencies are inferred from the claim text.