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US 7,605,044 B2Granted
Method of manufacturing semiconductor device
AssigneeDongbu HiTek Co., Ltd.
InventorJin-Ha Park
Life of this patent
Estimating the term…
Abstract
A method of manufacturing a semiconductor device including at least one step of: forming a transistor on and/or over a semiconductor substrate; forming silicide on and/or overa gate electrode and a source/drain region of the transistor; removing an uppermost oxide film from a spacer of the transistor; and forming a contact stop layer on and/or over the entire surface of the substrate including the gate electrode.
Claims11
A method comprising:
- forming a transistor over a semiconductor substrate, the transistor including a gate electrode, a source/drain region and a spacer having a laminated structure on sidewalls of the gate electrode including a first oxide film, a nitride film and a second oxide film;
- forming silicide over the gate electrode and the source/drain region;
- removing the second oxide film of the spacer;
- and
- forming a contact stop layer over the entire surface of the substrate including the gate electrode, wherein the contact stop layer is formed using a plasma enhanced chemical vapor deposition (PECVD) method, wherein the PECVD method is performed at a temperature range of between approximately 300 to 500° C. for 30 to 60 seconds with a bias power in a range between approximately 10 to 20 W and a ratio of SiH4 to NH3 in a range between 3:1 to 5:1, wherein the contact stop layer has at least one of tensile stress characteristics and compressive characteristics.
2 more elements
A method comprising:
- forming a transistor over a semiconductor substrate, the transistor including a gate electrode, a source/drain region and a spacer having a laminated structure on sidewalls of the gate electrode including a first oxide film, a nitride film and a second oxide film;
- forming silicide over the gate electrode and the source/drain region;
- removing the second oxide film of the spacer;
- and
- forming a contact stop layer over the entire surface of the substrate including the gate electrode, wherein the contact stop layer is formed using a plasma enhanced chemical vapor deposition (PECVD) method, wherein the contact stop layer has at least one of tensile stress characteristics and compressive characteristics, wherein:
- the transistor is an NMOS transistor;
- and
- the contact stop layer is formed by the PECVD method using a bias power in a range between approximately 10 to 12 W and a ratio of SiH4 to NH3 of 5:1 such that the contact stop layer has the tensile stress characteristic.
5 more elements
A method comprising:
- forming a transistor over a semiconductor substrate, the transistor including a gate electrode, a source/drain region and a spacer having a laminated structure on sidewalls of the gate electrode including a first oxide film, a nitride film and a second oxide film;
- forming silicide over the gate electrode and the source/drain region;
- removing the second oxide film of the spacer;
- and
- forming a contact stop layer over the entire surface of the substrate including the gate electrode, wherein the contact stop layer is formed using a plasma enhanced chemical vapor deposition (PECVD) method, wherein the contact stop layer has at least one of tensile stress characteristics and compressive characteristics, wherein,
- the transistor is a PMOS transistor;
- and
- the contact stop layer is formed by PECVD using a bias power in a range between approximately 18 to 20 W and a ratio of SiH4 to NH3 of 3:1 such that the contact stop layer has the compressive stress characteristic.
5 more elements
Dependencies are inferred from the claim text.