Semiconductor device and manufacturing method thereof

A manufacturing method of a semiconductor device having a high voltage region and a low voltage region, comprising:

• forming a device isolating layer isolating a high voltage region and a low voltage region on a semiconductor substrate;
• forming a first gate insulating film pattern on the semiconductor substrate in the high voltage region and a first gate electrode on the first gate insulating film pattern, and a second gate insulating film pattern on the semiconductor substrate in the low voltage region and a second gate electrode on the second gate insulating film pattern;
• forming a lightly doped drain (LDD) region in the low voltage region;
• forming an insulating film on the high voltage region and the low voltage region;
• forming a photoresist pattern on the insulating film, wherein the photoresist pattern covers one side of the first gate electrode and extending a first distance on a portion of the semiconductor substrate adjacent the one side of the first gate electrode and a second side of the first gate electrode and extending a second distance on a portion of the semiconductor substrate adjacent the second side of the first gate electrode, wherein the insulating film on remaining portions of the semiconductor substrate, including on the device isolating layer, is exposed;
• forming a first gate spacer on the first gate electrode and extending the first distance and the second distance on the adjacent portions of the semiconductor substrate and a second gate spacer on the second gate electrode by etching the insulating film using the photoresist pattern as a mask;
• forming a first source and drain region in the high voltage region and the second source and drain region in the low voltage region by ion-implanting the semiconductor substrate at high concentration using the first gate spacer and the second gate spacer as a mask;
• forming a metal film over the semiconductor substrate;
• and
• forming a silicide on the first source and drain region, the first gate electrode, and the second source and drain region by performing a rapid thermal processing.