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US 7,605,028 B2Granted
Method of forming a memory device having a storage transistor
AssigneeMicron Technology, Inc.
InventorChandra Mouli
Life of this patent
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Abstract
A memory device and a method of forming the memory device. The memory device comprises a storage transistor at a surface of a substrate comprising a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line connected to the gate structure. The memory device does not require an additional capacitive storage element.
Claims39
A method of forming a memory device, the method comprising:
- forming a partially depleted storage transistor at a surface of a substrate, the act of forming the partially depleted storage transistor comprising:
- forming a body portion protruding from a surface of the substrate,
- forming a first source/drain region of a first conductivity type on a side of the body portion,
- forming a second source/drain region of the first conductivity type on an opposing side of the body portion from the first source/drain region, and
- forming a gate structure wrapping at least partially around the body portion in at least two spatial planes;
- forming a bit line connected to the first source/drain region;
- and
- forming a word line connected to the gate structure,
- wherein the act of forming the storage transistor comprises forming a FinFet.
6 more elements
A method of forming a memory device, the method comprising:
- forming a partially depleted storage transistor at a surface of a substrate,
- the act of forming the partially depleted storage transistor comprising:
- forming a body portion protruding from a surface of the substrate,
- forming a first source/drain region of a first conductivity type on a side of the body portion,
- forming a second source/drain region of the first conductivity type on an opposing side of the body portion from the first source/drain region, and
- forming a gate structure wrapping at least partially around the body portion in at least two spatial planes;
- forming a bit line connected to the first source/drain region;
- and
- forming a word line connected to the gate structure,
- wherein the act of forming the storage transistor comprises forming the storage transistor at a surface of a silicon-on-insulator substrate.
7 more elements
A method of forming a memory device, the method comprising:
- forming a partially depleted storage transistor at a surface of a substrate,
- the act of forming the partially depleted storage transistor comprising:
- forming a body portion protruding from a surface of the substrate,
- forming a first source/drain region of a first conductivity type on a side of the body portion,
- forming a second source/drain region of the first conductivity type on an opposing side of the body portion from the first source/drain region, and
- forming a gate structure wrapping at least partially around the body portion in at least two spatial planes;
- forming a bit line connected to the first source/drain region;
- and
- forming a word line connected to the gate structure,
- wherein the act of forming the storage transistor further comprises forming a heavily doped region of a second conductivity type adjacent to the second source/drain region and separated from the first source/drain region.
7 more elements
A method of forming a memory device, the method comprising:
- forming a partially depleted storage transistor at a surface of a substrate,
- the act of forming the partially depleted storage transistor comprising:
- forming a body portion protruding from a surface of the substrate,
- forming a first source/drain region of a first conductivity type on a side of the body portion,
- forming a second source/drain region of the first conductivity type on an opposing side of the body portion from the first source/drain region, and
- forming a gate structure wrapping at least partially around the body portion in at least two spatial planes;
- forming a bit line connected to the first source/drain region;
- and
- forming a word line connected to the gate structure,
- wherein the act of forming the storage transistor further comprises forming an inert dopant region heavily doped with inert ions adjacent to the first source/drain region and separated from the second source/drain region.
7 more elements
A method of forming a memory device, the method comprising:
- forming a partially depleted storage transistor at a surface of a substrate,
- the act of forming the partially depleted storage transistor comprising:
- forming a body portion protruding from a surface of the substrate,
- forming a first source/drain region of a first conductivity type on a side of the body portion,
- forming a second source/drain region of the first conductivity type on an opposing side of the body portion from the first source/drain region, and
- forming a gate structure wrapping at least partially around the body portion in at least two spatial planes;
- forming a bit line connected to the first source/drain region;
- and
- forming a word line connected to the gate structure,
- wherein the act of forming the storage transistor further comprises forming a higher Schottky barrier between the second source/drain region and the body portion than a Schottky barrier between the body portion and the first source/drain region.
7 more elements
A method of forming a memory device, the method comprising:
- forming a partially depleted storage transistor at a surface of a substrate,
- the act of forming the partially depleted storage transistor comprising:
- forming a body portion protruding from a surface of the substrate,
- forming a first source/drain region of a first conductivity type on a side of the body portion,
- forming a second source/drain region of the first conductivity type on an opposing side of the body portion from the first source/drain region, and
- forming a gate structure wrapping at least partially around the body portion in at least two spatial planes;
- forming a bit line connected to the first source/drain region;
- and
- forming a word line connected to the gate structure,
- wherein the acts of forming the first and second source/drain regions comprise growing at least one epitaxial layer such that the first and second source/drain regions share a same horizontal spatial plane as the portion of the gate structure on a sidewall of the body portion.
7 more elements
A method of forming a memory device, the method comprising:
- forming a partially depleted storage transistor at a surface of a substrate,
- the act of forming the partially depleted storage transistor comprising:
- forming a body portion protruding from a surface of the substrate,
- forming a first source/drain region of a first conductivity type on a side of the body portion,
- forming a second source/drain region of the first conductivity type on an opposing side of the body portion from the first source/drain region, and
- forming a gate structure wrapping at least partially around the body portion in at least two spatial planes;
- forming a bit line connected to the first source/drain region;
- and
- forming a word line connected to the gate structure,
- wherein the acts of forming each of the first and second source/drain regions comprise forming a plurality of layers, the act of forming the plurality of layers comprising forming at least one layer of a first material and at least one layer of a second material.
7 more elements
A method of fabricating a partially depleted storage transistor, the method comprising:
- forming at least one fin-shaped structure protruding from a surface of the substrate, the at least one fin-shaped structure forming at least a portion of a channel region of the partially depleted storage transistor;
- forming a first source/drain region of a first conductivity type on a side of the at least one fin-shaped structure;
- forming a second source/drain region of a first conductivity type on a side of the at least one fin-shaped structure opposite to the first source/drain region;
- forming a region of a second conductivity type in the substrate adjacent to the second source/drain region and separated from the first source/drain region;
- and
- forming a gate structure, wherein the gate structure wraps at least partially around the at least one fin-shaped structure in at least two spatial planes,
- wherein the act of forming the at least one fin-shaped structure comprises forming the at least one structure protruding from a surface of a silicon-on-insulator substrate.
4 more elements
A method of fabricating a partially depleted storage transistor, the method comprising:
- forming at least one fin-shaped structure protruding from a surface of the substrate, the at least one fin-shaped structure forming at least a portion of a channel region of the partially depleted storage transistor;
- forming a first source/drain region of a first conductivity type on a side of the at least one fin-shaped structure;
- forming a second source/drain region of a first conductivity type on a side of the at least one fin-shaped structure opposite to the first source/drain region;
- forming a region of a second conductivity type in the substrate adjacent to the second source/drain region and separated from the first source/drain region;
- forming a gate structure, wherein the gate structure wraps at least partially around the at least one fin-shaped structure in at least two spatial planes;
- and
- forming an inert dopant region heavily doped with inert ions adjacent to the first source/drain region and separated from the second source/drain region.
4 more elements
A method of fabricating a partially depleted storage transistor, the method comprising:
- forming at least one fin-shaped structure protruding from a surface of the substrate, the at least one fin-shaped structure forming at least a portion of a channel region of the partially depleted storage transistor;
- forming a first source/drain region of a first conductivity type on a side of the at least one fin-shaped structure;
- forming a second source/drain region of a first conductivity type on a side of the at least one fin-shaped structure opposite to the first source/drain region;
- forming a region of a second conductivity type in the substrate adjacent to the second source/drain region and separated from the first source/drain region;
- forming a gate structure, wherein the gate structure wraps at least partially around the at least one fin-shaped structure in at least two spatial planes;
- and
- forming a higher Schottky barrier between the second source/drain region and the at least one fin-shaped structure than a Schottky barrier between the at least one fin-shaped structure and the first source/drain region.
4 more elements
A method of fabricating a partially depleted storage transistor, the method comprising:
- forming at least one fin-shaped structure protruding from a surface of the substrate, the at least one fin-shaped structure forming at least a portion of a channel region of the partially depleted storage transistor;
- forming a first source/drain region of a first conductivity type on a side of the at least one fin-shaped structure;
- forming a second source/drain region of a first conductivity type on a side of the at least one fin-shaped structure opposite to the first source/drain region;
- forming a region of a second conductivity type in the substrate adjacent to the second source/drain region and separated from the first source/drain region;
- and
- forming a gate structure, wherein the gate structure wraps at least partially around the at least one fin-shaped structure in at least two spatial planes,
- wherein the acts of forming the first and second source/drain regions comprise growing at least one epitaxial layer such that the first and second source/drain regions share a same horizontal spatial plane as the portion of the gate structure on a sidewall of the at least one fin-shaped structure.
4 more elements
A method of fabricating a partially depleted storage transistor, the method comprising:
- forming at least one fin-shaped structure protruding from a surface of the substrate, the at least one fin-shaped structure forming at least a portion of a channel region of the partially depleted storage transistor;
- forming a first source/drain region of a first conductivity type on a side of the at least one fin-shaped structure;
- forming a second source/drain region of a first conductivity type on a side of the at least one fin-shaped structure opposite to the first source/drain region;
- forming a region of a second conductivity type in the substrate adjacent to the second source/drain region and separated from the first source/drain region;
- and
- forming a gate structure, wherein the gate structure wraps at least partially around the at least one fin-shaped structure in at least two spatial planes,
- wherein the acts of forming each of the first and second source/drain regions comprise forming a plurality of layers, the act of forming the plurality of layers comprising forming at least one layer of a first material and at least one layer of a second material.
4 more elements
Dependencies are inferred from the claim text.