Semiconductor chip package
AssigneeAdvanced Semiconductor Engineering, Inc.
InventorsSu Tao, Shih Chang Lee
Life of this patent
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Abstract
A method of manufacturing a semiconductor chip package includes mechanically and electrically connecting a semiconductor chip to a top surface of a main substrate, securely attaching the semiconductor chip to a recessed cavity on a bottom surface of an interconnection substrate, mechanically and electrically connecting the main substrate to the interconnection substrate, and cutting the main substrate to form a central substrate and a peripheral substrate wherein the semiconductor chip is disposed on the central substrate. The cutting step is conducted either (i) by forming a plurality of slots such that the central substrate and the peripheral substrate are partially conned to each other or (ii) by completely separating the central substrate and the peripheral substrate.
Claims8
A method of manufacturing a semiconductor chip package, the method comprising the steps of:
- mechanically and electrically connecting a semiconductor chip to a top surface of a main substrate;
- securely attaching the semiconductor chip to a recessed cavity on a bottom surface of an interconnection substrate;
- mechanically and electrically connecting the main substrate with the semiconductor chip to the interconnection substrate;
- cutting the main substrate to form a central substrate and a peripheral substrate wherein the semiconductor chip is disposed on the central substrate;
- wherein the cutting step is conducted by forming a plurality of slots, without cutting the interconnection substrate, such that the central substrate and the peripheral substrate are partially conned to each other.
Dependencies are inferred from the claim text.