Automatic placement of decoupling capacitors

A process for designing an integrated circuit comprising:

• synthesizing a netlist of logic cells and wire connection between pins of the logic cells;
• within a given region of a plurality of regions in the integrated circuit, placing a layout of each logic cell in the given region in response to the netlist;
• determining, with a processor, the optimum decoupling capacitance for the given region in response to the placing of the layout of each logic cell in the given region;
• and
• placing a layout of one or more decoupling capacitance cells between power and ground in the given region if a sum of the inherent decoupling capacitance of the logic cells in the given region is less than the optimum decoupling capacitance for the given region.

A machine-readable product for designing an integrated circuit, the machine-readable product comprising:

• a machine readable storage device having stored therein
• machine readable program code to place one or more decoupling capacitance cells in a first region of a plurality of regions in an integrated circuit layout to couple to a power grid;
• machine readable program code to sum the inherent decoupling capacitance of each logic cell in the first region of the integrated circuit layout to determine the regional inherent decoupling capacitance;
• machine readable program code to determine the regionally needed decoupling capacitance for the first region;
• and
• machine readable program code to determine the difference between the regional inherent decoupling capacitance and the regionally needed decoupling capacitance to determine the optimum decoupling capacitance to place the one or more decoupling cells in the first region.

A system for designing an integrated circuit, the system comprising:

• a processor to execute instructions;
• a storage device coupled to the processor, the storage device including instructions stored therein that when executed cause the processor to
• generate a plurality of regions of an integrated circuit layout including a first region of the integrated circuit layout with one or more logic cells to couple to a power grid;
• statically analyze each of the one or more logic cells in the first region of the integrated circuit layout to determine an optimum amount of decoupling capacitance for the first region to compensate for a voltage drop in the power grid;
• and
• in response to the optimum amount of decoupling capacitance for the first region, add at least one decoupling capacitor cell to the integrated circuit layout in the first region to compensate for the voltage drop in the power grid.