Net/wiring selection method, net selection method, wiring selection method, and delay improvement method

A net selection apparatus for selecting, from among nets wired on the basis of layout information, at least one net whose layout is to be preferentially changed in order to improve a delay, said apparatus comprising:

• a wiring capacitance lower limit computation section computing wiring capacitance lower limits of respective wirings, on the basis of said layout information;
• an inter-wiring capacitance computation section computing, as an inter-wiring capacitance, a difference between a real wiring capacitance and said wiring capacitance lower limit computed by said wiring capacitance lower limit computation section;
• a parallel wiring length extraction section extracting a parallel wiring length existing between adjacent wirings belonging to said nets, on the basis of said layout information;
• a first net selection section selecting a first net whose slack value is less than a predetermined value, as said at least one net;
• a second net selection section selecting a second net as said at least one net, wherein a total of inter-wiring capacitances of all wirings belonging to each of said nets computed by said inter-wiring computation section is greater than or equal to a predetermined value;
• and
• a third net selection section selecting, as said at least one net, a third net having wirings whose parallel length extracted by said parallel wiring length extraction section is greater than or equal to a predetermined value.

A net selection program stored in a computer readable device, said net selection program, when executed by a computer, enabling said computer to perform a function of selecting, from among nets wired on the basis of layout information, at least one net whose layout is to be preferentially changed in order to improve a delay, said net selection program enabling said computer to implement:

• a wiring capacitance lower limit computation section computing wiring capacitance lower limits of respective wirings belonging to said nets, on the basis of said layout information;
• an inter-wiring capacitance computation section computing, as an inter-wiring capacitance, a difference between a real wiring capacitance and said wiring capacitance lower limit computed by said wiring capacitance lower limit computation section;
• a parallel wiring length extraction section extracting a parallel wiring length existing between adjacent wirings belonging to said nets, on the basis of said layout information;
• a first net selection section selecting a net whose slack value is less than a predetermined value, as said at least one net;
• a second net selection section selecting a second net as said at least one net, wherein a total of inter-wiring capacitances of all wirings belonging to each of said nets computed by said inter-wiring computation section is greater than or equal to a predetermined value;
• and
• a third net selection section selecting, as said at least one net, a third net having wirings whose parallel length extracted by said parallel wiring length extraction section is greater than or equal to a predetermined value.

A delay improvement program stored in a computer readable device, said delay improvement program, when executed by a computer, enabling said computer to perform a function of changing a layout by means of selecting, from among wirings wired on the basis of layout information, a wiring whose layout is to be preferentially changed in order to improve a delay, said delay improvement program enabling said computer to implement:

• a wiring capacitance lower limit computation section computing wiring capacitance lower limits of respective wirings on the basis of said layout information;
• an inter-wiring capacitance computation section computing, as an inter-wiring capacitance, a difference between a real wiring capacitance and said wiring capacitance lower limit computed by said wiring capacitance lower limit computation section;
• a parallel wiring length extraction section extracting a parallel wiring length existing between adjacent wirings of said respective wirings, on the basis of said layout information;
• a net selection section selecting a net whose layout is to be changed, on the basis of a total of said inter-wiring capacitances of all wirings belonging to said net which have been computed by said inter-wiring capacitance computation section, said parallel wiring lengths of said respective wirings belonging to said net extracted by said parallel wiring extraction section, and a slack value of said net;
• a wiring selection section selecting, from among wirings belonging to said net selected by said net selection section, a wiring whose layout is to be changed on the basis of said inter-wiring capacitance, said parallel wiring length, and a slack value of a wiring;
• and
• a layout change section changing a layout of said wiring selected by said wiring selection section.