Iterative metric updating when decoding LDPC (low density parity check) coded signals and LDPC coded modulation signals

A method for operating a decoder to decode an LDPC (Low Density Parity Check) coded signal, the method comprising:

• during a first decoding iteration:
• employing a bit node processing module to perform bit node processing that involves using a first plurality of bit metrics when updating a first plurality of bit messages thereby generating a second plurality of bit edge messages, wherein the first plurality of bit metrics corresponds to a bit within the LDPC coded signal;
• employing a check node processing module to perform check node processing that involves using the second plurality of bit edge messages when updating a first plurality of check edge messages thereby generating a second plurality of check edge messages;
• and
• computing a first soft estimate of the bit within the LDPC coded signal using the second plurality of check edge messages;
• and
• during a second decoding iteration:
• updating the first plurality of bit metrics using the soft estimate thereby generating a second plurality of bit metrics;
• employing the bit node processing module to perform bit node processing that involves using the second plurality of bit metrics when updating the second plurality of bit messages thereby generating a third plurality of bit edge messages;
• employing the check node processing module to perform check node processing that involves using the third plurality of bit edge messages when updating the second plurality of check edge messages thereby generating a third plurality of check edge messages;
• and
• computing a second soft estimate of the bit within the LDPC coded signal using the third plurality of check edge messages.

A decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal, the decoder comprising:

• a bit node processing module that is operable to employ a first plurality of bit metrics when updating a first plurality of bit edge messages thereby generating a second plurality of bit edge messages, wherein the plurality of bit metrics corresponds to a bit within the LDPC coded signal;
• and
• a check node processing module that is operable to employ the second plurality of bit edge messages when updating a first plurality of check edge messages thereby generating a second plurality of check edge messages;
• and wherein:
• the bit node processing module is operable to process the second plurality of check edge messages thereby generating a first soft estimate of the bit within the LDPC coded signal;
• the decoder is operable to update the first plurality of bit metrics using the first soft estimate thereby generating a second plurality of bit metrics;
• the bit node processing module is operable to employ the second plurality of bit metrics when updating the second plurality of bit edge messages thereby generating a third plurality of bit edge messages;
• the check node processing module is operable to employ the third plurality of bit edge messages when updating the second plurality of check edge messages thereby generating a third plurality of check edge messages;
• and
• the bit node processing module is operable to process the third plurality of check edge messages thereby generating a second soft estimate of the bit within the LDPC coded signal.