Delta syndrome based iterative Reed-Solomon product code decoder

A circuit comprising:

• a row syndrome module configured to calculate a plurality of first row syndromes from a first block of first data arranged as a Reed-Solomon product code and received from a source at an input of said circuit;
• a buffering module configured to (i) store said first data as received at said input in a first buffer and (ii) apply row error correction information to said first data as stored, wherein said first buffer holds at most a first fraction of said first block;
• a column syndrome module configured to calculate an initial set of values of a plurality of first column syndromes from said first block as read from said first buffer after said row error correction information has been applied;
• a local memory coupled to said row syndrome module and said column syndrome module, said local memory configured to (i) store both said first row syndromes and said first column syndromes of said first block;
• a decoder module configured to (a) generate said row error correction information by decoding said first row syndromes (b) decode in a sequence alternating between a first pass and a second pass, wherein (i) said first pass comprises decoding using only said first column syndromes to generate column correction results and (ii) said second pass comprises decoding using only said first row syndromes to generate row correction results and (c) generate both a plurality of row corrections and a plurality of column corrections in response to said first row syndromes and said first column syndromes and to store row corrections and column corrections in the local memory;
• a dispatcher module configured to dispatch first row syndromes and/or first column syndromes from the local memory periodically to the decoder module;
• a delta syndrome module configured to (i) update said first row syndromes in response to said column correction results stored in local memory and (ii) update said first column syndromes in response to said row correction results;
• and
• a correction module configured to (i) store said first data a second buffer, (ii) generate corrected data by correcting said first data as stored in said second buffer using both said row corrections and said column corrections and (iii) generate an output signal carrying said corrected data, wherein said first data as written into said first buffer after said row error correction information has been applied matches said first data as written into said second buffer after generation of all of said row corrections and said column corrections.

A circuit comprising:

• row syndrome means for calculating a plurality of first row syndromes from a first block of first data arranged as a Reed-Solomon product code and received from a source at an input of said circuit;
• means for (i) storing said first data as received at said input in a first buffer and (ii) applying row error correction information to said first data as stored, wherein said first buffer holds at most a first fraction of said first block;
• column syndrome means for calculating an initial set of values of a plurality of first column syndromes from said first block as read from said first buffer after said row error correction information has been applied;
• a local memory means coupled to said row syndrome means and said column syndrome means, said local memory means configured to (i) store both said first row syndromes and said first column syndromes of said first block;
• a decoding means for (a) generating said row error correction information by decoding said first row syndromes (b) decoding in a sequence alternating between a first pass and a second pass, wherein (i) said first pass comprises decoding using only said first column syndromes to generate column correction results and (ii) said second pass comprises decoding using only said first row syndromes to generate row correction results and (c) generate both a plurality of row corrections and a plurality of column corrections in response to said first row syndromes and said first column syndromes;
• a means for dispatching first row syndromes and/or first column syndromes from the local memory means periodically to the decoder means;
• means for (i) updating said first row syndromes in response to said column correction results stored in local memory means and (ii) updating said first column syndromes in response to said row correction results and
• means for (i) storing said first data in a second buffer, (ii) generating corrected data by correcting said first data as stored in said second buffer using both said row corrections and said column corrections and (iii) generating an output signal carrying said corrected data, wherein said first data as written into said first buffer after said row error correction information has been applied matches said first data as written into said second buffer after generation of all of said row corrections and said column corrections.