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US 7,600,167 B2Granted
Flip-flop, shift register, and scan test circuit
AssigneeNEC Corporation
InventorHiroaki Shoda
Life of this patent
Estimating the term…
Abstract
A flip-flop has a first latch and a second latch. The first latch has a first feedback circuit and a first selecting circuit which selects one of a first data input signal and an output signal of the first feedback circuit, based on the logic level of a first clock signal. The second latch has a second feedback circuit and a second selecting circuit which selects an output signal of the first latch and an output signal of the second feedback circuit based on the inverted logic level in case of the first latch. The first feedback circuit has a third selecting circuit which selects one of an output signal of the first latch and a second data input signal based on the logic level of a second clock signal, and outputs a signal selected by the third selecting circuit to the first selecting circuit.
Claims20
A flip-flop, comprising:
- a first latch which includes a first feedback circuit which feedbacks a output signal of the first latch to an input of the first latch, and a first selecting circuit which selects a first data input signal of the first latch when a first clock signal is a first logic level and selects an output signal of the first feedback circuit when the first clock signal is a first inverted logic level of the first logic level;
- and
- a second latch which includes a second feedback circuit which feedbacks a output signal of the second latch to an input of the second latch, and a second selecting circuit which selects an output signal of the first latch when the first clock signal is the first inverted logic level and selects an output signal of the second feedback circuit when the first clock signal is the first logic level;
- wherein the first feedback circuit comprises a third selecting circuit which selects an output signal of the first latch when a second clock signal is a second logic level and selects a second data input signal of the first latch when the second clock signal is a second inverted logic level of the second logic level, and outputs a signal selected by the third selecting circuit to the first selecting circuit.
1 more element
A flip-flop, comprising:
- a first latch which includes a first feedback circuit which feedbacks a output signal of the first latch to a input of the first latch, and a first selecting circuit which selects a first data input signal of the first latch when a first clock signal is a first logic level and selects an output signal of the first feedback circuit when the first clock signal is a first inverted logic level of the first logic level;
- a second latch which includes a second feedback circuit which feedbacks a output signal of the second latch to a input of the second latch, and a second selecting circuit which selects an output signal of the first latch when the first clock signal is the first inverted logic level and selects an output signal of the second feedback circuit when the first clock signal is the first logic level;
- and
- a third latch which includes a third feedback circuit which feedbacks a output signal of the third latch to an input of the third latch, and a third selecting circuit which selects a second input signal of the third latch when a second clock signal is a second logic level and selects an output signal of the third feedback circuit when the second clock signal is the second inverted logic level;
- wherein the first feedback circuit comprises a forth selecting circuit which selects an output signal of the first latch when the second clock signal is the second logic level and selects an output signal of the third latch when the second clock signal is the second inverted logic level, and outputs a signal selected by the forth selecting circuit to the first selecting circuit.
2 more elements
A flip-flop, comprising:
- a first latch including a first feedback circuit, a first selecting circuit and a second selecting circuit;
- and
- a second latch including a second feedback circuit and a third selecting circuit,
- wherein the first selecting circuit inputs a first data input signal of the first latch and an output signal of the second selecting circuit and selects one of the first data input signal and the output signal of the second selecting circuit according to a logic level of a first clock signal to output to the second latch and the first feedback circuit,
- wherein the second selecting circuit inputs a second data input signal of the first latch and an output signal of the first feedback circuit being fed back and selects one of the second data input signal and the output signal of the first feedback circuit according to a logic level of a second clock signal to output to the first selecting circuit, and
- wherein the third selecting circuit inputs an output signal of the first latch and an output signal of the second feedback circuit being fed back and selects one of the output signal of the first latch and the output signal of the second feedback circuit according to an inverted condition of the logic level of the first clock signal used in the first latch to output to the second feedback circuit.
3 more elements
A flip-flop, comprising:
- a first latch including a first feedback circuit, a first selecting circuit and a second selecting circuit;
- and
- a second latch including a second feedback circuit and a third selecting circuit,
- wherein an input of the first feedback circuit is coupled with an output of the first latch
- wherein an output of the first selecting circuit is coupled with the output of the first latch,
- wherein a feedback output of the first feedback circuit is coupled with one of inputs of the second selecting circuit,
- wherein an output of the second selecting circuit is coupled with one of inputs of the first selecting circuit,
- wherein a first data input of the first latch is coupled with another input of the first selecting circuit, and
- wherein a second data input of the first latch is coupled with another input of the second selecting circuit,
- wherein the first selecting circuit selects one of the first data input and the output of the second selecting circuit according to a logic level of a first clock signal,
- wherein the second selecting circuit selects one of the second data input and the feedback output of the first feedback circuit according to a logic level of a second clock signal,
- wherein an output of the third selecting circuit is coupled with an output of the second latch,
- wherein an input of the second feedback circuit is coupled with the output of the second latch,
- wherein a feedback output of the second feedback circuit is coupled with one of inputs of the third selecting circuit,
- wherein an output of the first latch is coupled with another input of the third selecting circuit,
- wherein the third selecting circuit selects one of the output of the second feedback circuit and the output of the first latch according to an inverted condition of the logic level of the first clock signal used in the first latch.
13 more elements
Dependencies are inferred from the claim text.