Method and system for providing trusted access to a JTAG scan interface in a microprocessor

A system for securing a scan chain architecture, comprising:

• a secure processor;
• a JTAG scan interface coupled to said secure processor that is capable of accessing secure features of said secure processor;
• a trusted software communicatively coupled to said secure processor for validating an authentication message, wherein said trusted software has authorized access to trusted resources in said secure processor;
• a communication buffer for receiving said authentication message, herein said communication buffer provides an interface to said trusted software for authentication purposes;
• an authentication link that communicatively couples said communication buffer directly to said trusted software for authentication purposes;
• and
• a register internal to said secure processor for enabling said JTAG scan interface when properly set, wherein said trusted software enables said register when said authentication message is valid.

A computer system comprising:

• a processor for processing information;
• and
• a computer readable memory coupled to said processor and containing program instructions that, when executed cause said processor to implement a method for securing a scan chain architecture, comprising:
• disabling by default a JTAG scan interface in a system comprising a secure processor and a trusted software layer that has authorized access to trusted resources in said secure processor, wherein said JTAG scan interface is capable of accessing trusted features of said secure processor;
• receiving an authentication message at the trusted software layer, wherein said authentication message when valid provides access to said JTAG scan interface;
• verifying said authentication message is valid using said trusted software layer;
• and
• enabling said JTAG scan interface when said authentication message is valid using said trusted software layer.