Error control coding method and system for non-volatile memory
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorYue Der Chih
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Abstract
Methods and systems for improving repairing efficiency in non-volatile memory. Repairing data may be read from an information array associated with the non-volatile memory. The repairing data is generally read to a volatile latch associated with the non-volatile memory. An error correction coding circuit (ECC) circuit can be enabled during reading of the repairing data for identifying and repairing defective columns or rows associated with the non-volatile memory, despite errors in the repairing data read out.
Claims13
A method for improving repairing efficiency in a non-volatile memory, said method comprising the steps of:
- reading repairing data from an information array associated with said non-volatile memory to a volatile latch array associated with said non-volatile memory, said information array sharing a read circuit with a main memory array comprising said non-volatile memory;
- enabling an error correction coding circuit separate from said information array during reading of said repairing data including corrupted repairing data located anywhere in said information array, said repairing data for identifying and repairing defective columns or rows comprising said main memory array despite corruption of the repairing data as read;
- providing a plurality of columns and rows associated with said non-volatile memory;
- associating each of said plurality of columns associated with said non-volatile memory with a respective I/O terminal;
- and
- using a (16,11) Hamming code to associate at least one spare column with at least two of each of said plurality of columns associated with both said non-volatile memory and with a respective I/O terminal.
A system for improving repairing efficiency in a non-volatile memory, said system comprising:
- a reading circuit for reading repairing data from an information array associated with said non-volatile memory to a volatile latch array associated with said non-volatile memory, said information array sharing said read circuit with a main memory array comprising said non-volatile memory;
- an error correction coding circuit separate from said information array adapted to be enabled during reading of said repairing data including reading corrupted repairing data located anywhere in said information array, said repairing data for identifying and repairing defective columns or rows comprising said main memory array despite corruption of the repairing data as read;
- a plurality of columns and rows each associated with said non-volatile memory, wherein each of said plurality of associated columns and rows is further associated with a respective I/O terminal;
- and
- a spare column, wherein said error correction coding circuit using a (16,11) Hamming code to associate said spare column with at least two of each of said plurality of columns associated with both said non-volatile memory and with a respective I/O terminal.
Dependencies are inferred from the claim text.