Convolutional interleaver and deinterleaver
AssigneeRealtek Semiconductor Corp.
InventorsBin Wan, Chia-Liang Lin
Life of this patent
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Abstract
An apparatus for receiving and storing an incoming sequence and for forwarding the bytes of the incoming sequence as an outgoing sequence in a different byte order includes a cache memory and a main memory for storing bytes of the incoming sequence until they can be forwarded as bytes of the outgoing sequence. A control circuit selectively burst mode writes sequences of incoming bytes that need be stored for a relatively long time to blocks of sequential addresses of the main memory, writes individual bytes of the incoming sequence that need be stored for a relatively short time to selected addresses of the cache memory, and reads bytes out of the cache memory and the main memory when needed to form the outgoing sequence.
Claims25
An apparatus for forming a sequence of N-byte second words from bytes forming a sequence of N-byte first words, where N is any integer greater than 1, the apparatus comprising:
- a main memory for storing a plurality of bytes, each at a separate address;
- a cache memory for storing a plurality of bytes, each at a separate address, wherein the size of the main memory is larger than that of the cache memory;
- and
- a control circuit, coupled to the main memory and the cache memory, for comparing the size of the cache memory with a product of the data length, N and a desired interleaving/de-interleaving depth, D to produce a control signal, for writing bytes of each first word into either the main memory or the cache memory according to the control signal, for reading bytes out of the cache memory or the main memory and forming each second word according to the control signal such that each second word comprises the bytes of more than one of the first words.
A method for forming a sequence of N-byte second words from bytes forming a sequence of N-byte first words, wherein N is any integer greater than 1, the method comprising the steps of:
- comparing the size of the cache memory with a product of the data length, N and a desired interleaving/de-interleaving depth, D to produce a control signal,
- writing bytes of each first word into a main memory or into a cache memory according to the control signal,
- transferring bytes between the main memory and the cache memory according to the control signal, and
- reading bytes of the cache memory or the main memory and forming each second word according to the control signal such that each second word comprises the bytes of more than one of the first words.
Dependencies are inferred from the claim text.