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US 7,600,145 B2Granted
Clustered variations-aware architecture
AssigneeIntel Corporation
InventorsXavier Vera, Oguz Ergin, Osman Unsal, Antonio Gonzalez
Life of this patent
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Abstract
Methods and apparatus to provide a clustered variations-aware architecture are described. In one embodiment, one or more variations within a clock domain are detected and utilized to adjust a clock signal of the clock domain.
Claims27
A method comprising:
- detecting one or more variations within a clock domain of a plurality of clock domains of a processor;
- adjusting a clock signal of the clock domain in response to the one or more variations;
- comparing a speculative output of a pipeline stage of the processor with a correct output of the pipeline stage of the processor;
- and
- determining whether the speculative output matches the correct output.
2 more elements
An apparatus comprising:
- logic to detect one or more variations within a clock domain of a plurality of clock domains of a processor;
- a frequency controller to adjust a clock signal of the clock domain in response to the one or more variations;
- and
- a comparison logic to compare a speculative output of a pipeline stage of the processor with a correct output of the pipeline stage of the processor to determine whether the speculative output matches the correct output.
1 more element
A processor comprising:
- a first domain to receive a first clock signal;
- a second domain to receive a second clock signal;
- one or more sensors to detect one or more variations within the first domain and the second domain;
- a first logic to adjust a frequency of the first clock in response to the one or more variations within the first domain;
- a second logic to adjust a frequency of the second clock in response to the one or more variations within the second domain;
- and
- a comparison logic to compare a speculative output of a pipeline stage of the processor with a correct output of the pipeline stage of the processor to determine whether the speculative output matches the correct output.
4 more elements
A computing system comprising:
- one or more domains, each domain comprising:
- logic to perform one or more computing functions;
- one or more sensors coupled to one or more components of the logic to perform the one or more computing functions, the one or more sensors to sense variations within a corresponding domain;
- a frequency controller coupled to the logic to perform the one or more computing functions and the one or more sensors, the frequency controller to adjust a frequency of a clock signal for the corresponding domain in response to one or more of timing errors or variations;
- and
- a comparison logic to compare a speculative output of a pipeline stage of a processor with a correct output of the pipeline stage of the processor to determine whether the speculative output matches the correct output.
3 more elements
Dependencies are inferred from the claim text.