Method and apparatus for variable delay data transfer
AssigneeUnisys Corporation
InventorPaul S. Neuman
Life of this patent
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Abstract
A method and apparatus allows data to traverse a cache interface device in one of four transfer modes. A fast bypass mode provides received cache data within the same master clock cycle as it was received, whereas a slow bypass mode provides received cache data within the subsequent master clock cycle. A queue mode provides a programmable amount of delay to be used by the cache interface device, whereby consecutive queue mode provides a First In First Out (FIFO) operation to consecutively retrieve queued data. A block queue mode, on the other hand, provides a method to retrieve queued data using a programmable offset so as to enable partial cache line retrieval without the need to use No Operation (NoP) clock cycles on the cache interface data bus.
Claims16
A method of data transfer using programmable delay, comprising:
- providing a plurality of alternative data paths, each of the data paths being programmably selectable based on a state of one or more control signals, and each of the data paths providing a different data transfer delay to reach an output register;
- receiving a data block at a first instant in time within a first master clock cycle;
- determining one of a plurality of master clock cycles to be used as a second master clock cycle;
- programmably selecting one of the alternative data paths based on the state of the one or more control signals to utilize its corresponding data transfer delay in providing the data block to the output register to accommodate a data storage mechanism between an external cache and a front side bus, wherein at least one of the data transfer delays comprises an amount of time greater than the first master clock cycle;
- and
- transmitting the received data block from the output register at a second instant in time within the second master clock cycle.
An apparatus coupled to a data storage mechanism between an external cache and a front side bus, the apparatus comprising:
- an output register;
- an input register configured to receive a data block;
- a plurality of alternative data paths each suitable for transferring the data block from the input register to the output register in accordance with a master clock signal;
- a controller having inputs to receive control signals, wherein different states of the control signals respectively correspond to different delay modes to accommodate the data storage mechanism, and having outputs to activate one of the plurality of alternative data paths to programmably effect a desired one of the delay modes based on the state of the control signals;
- and
- wherein the activated one of the data paths comprises means for delaying the transfer of the data block to the output register for a duration different than a transfer delay of the other data paths, and wherein at least one of the delay modes delays transfer of the data block by an amount of time greater than a single cycle of the master clock signal.
A method comprising:
- providing a plurality of alternative data paths for transferring a data block from an input to an output of a device in accordance with a master clock signal;
- providing a plurality of programmable delay modes, and wherein at least one of the programmable delay modes delays transfer of the data block by an amount of time greater than a single cycle of the master clock signal to accommodate a data storage mechanism between an external cache and a front side bus;
- receiving the data block at the input of the device;
- selecting one of the different data paths in which to direct the data block as a function of which of the configurable delay modes is active;
- and
- delaying delivery of the data block to the output of the device for a time that is dependent upon the selected data path that has been selected as a function of the active configurable delay modes.
Dependencies are inferred from the claim text.