Condition bits for controlling branch processing
AssigneeBroadcom Corporation
InventorSophie Wilson
Life of this patent
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Abstract
A processing pipeline with a plurality of pipeline stages is described, with the processing pipeline comprising a front end and a back end. The processing pipeline's front end comprises an array for storing at least two condition bits, the condition bits being adapted for indicating respective conditions. The front end is adapted for resolving conditional branch instructions by accessing the array of condition bits whenever a conditional branch instruction occurs, the respective branch instruction being resolved in accordance with a corresponding condition bit. In another embodiment, the condition bits are combined with predicated execution of instructions, with the instruction's predicates being evaluated at the processing pipeline's back end.
Claims21
A processing pipeline with a plurality of pipeline stages, the processing pipeline comprising:
- a front end comprising logic configured to resolve conditional branch instructions by accessing an array of condition bits whenever a conditional branch instruction occurs, the respective branch instruction being resolved in accordance with a corresponding condition bit;
- a scoreboard having at least one scoreboard bit per condition bit, wherein each scoreboard bit is configured to indicate whether a corresponding condition bit is valid or whether a corresponding condition bit is in the process of being up-dated;
- and
- a back end comprising logic configured to handle predicated instructions.
A method for implementing conditional execution of instructions, the method comprising:
- resolving a conditional branch instruction at a front end of a processor pipeline by accessing condition bits stored in an array;
- indicating, with at least one scoreboard bit per condition bit, whether a condition bit is valid or whether a condition bit is in the process of being up-dated;
- and
- evaluating a predicate of a predicate instruction at a back end of the processor pipeline.
Dependencies are inferred from the claim text.