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US 7,600,101 B2Granted
Multithreaded hardware systems and methods
AssigneeHewlett-Packard Development Company, L.P.
InventorDonald C. Soltis, Jr.
Life of this patent
Estimating the term…
Abstract
Multithreaded hardware systems and methods are disclosed. One embodiment of a system may comprise a multithreaded processor comprising a register file having N hardware threads, where N is an integer greater than or equal to one, and an offline storage structure having M hardware threads, where M is an integer greater than or equal to one. The multithreaded processor system may further comprise a thread control that transfers register values associated with at least one of the N hardware threads to registers of at least one of the M hardware threads and transfers register values of at least of one of the M hardware threads to registers of at least one of the N hardware threads.
Claims27
A multithreaded processor system comprising:
- a register file having N hardware threads, where N is an integer greater than one;
- an offline storage structure having M hardware threads, where M is an integer greater than or equal to one;
- and
- a thread control that inactivates a first one of the N hardware threads in the register file and activates a second one of the N hardware threads in the register file and, in response to the inactivation of the first one of the N hardware threads and the activation of the second one of the N hardware threads, unloads register values associated with a first architected state of the processor system from the inactivated thread to registers of one of the M hardware threads and loads register values from one of the M hardware threads associated with a second architected state of the processor system to the inactivated thread in the register file;
- wherein the register file is arranged as columns of registers with each column having N register portions, such that each of the N register portions is associated with a different hardware thread of the register file;
- wherein the offline storage structure is an offline register file arranged as columns of registers with each column having M register portions, such that each of the M register portions is associated with a different hardware thread of the offline register file;
- and
- wherein the M register portions and the N register portions are shift registers and a given column of M register portions associated with a respective register in the offline register file is aligned with a given column of N register portions associated with a substantially similar register in the register file, such that a shift register ring is formed that allows for the shifting register values from the one of the M hardware threads in the offline register file to the first one of the N hardware threads in the register file concurrently with the shifting of register values from the first one of the N hardware threads in the register file to the one of the M hardware threads in the offline register file.
5 more elements
A multithreaded register file architecture comprising:
- a register file having a plurality of hardware threads and associated control logic for reading and writing of register values associated with an active hardware thread of the register file;
- an offline thread structure having at least one offline hardware thread for storing register values associated with an architected state of at least one inactive hardware thread of the register file;
- and
- a thread control that initiates the transfer of register values between at least one inactive thread of the register file and the at least one offline hardware thread of the offline thread structure by aligning one of the at least one inactive hardware thread in the register file with one of the at least one inactive hardware thread in the offline thread structure to form a shift register ring, such that register values of the one of the at least one inactive thread of the register file are transferred to the one of the at least one inactive hardware thread in the offline thread structure and register values of the one of the at least one inactive hardware thread in the offline thread structure are transferred to the one of the at least one inactive thread of the register file concurrently.
1 more element
A register file system having a register file with at least one hardware threads, the system comprising:
- means for storing architected states of registers associated with at least one hardware thread of the register file offline from the register file;
- and
- means for controlling the transfer of register values of an architected state of a register concurrently between the register file and the means for storing architected states in response to an inactivation of a hardware thread that is associated with the architected state of the register.
A method for storing architected states associated with registers of a register file, the method comprising:
- inactivating a first hardware thread of a register file;
- activating a second hardware thread of a register file;
- unloading register values from the first hardware thread of a register file to a hardware thread in an offline thread structure;
- and
- loading register values from the hardware thread in the offline thread structure to the first hardware thread of the register file;
- wherein the unloading and loading is executed concurrently.
3 more elements
A multithreaded processor system comprising:
- a register file having N hardware threads, where N is an integer greater than one;
- an offline storage structure having M hardware threads, where M is an integer greater than or equal to one;
- and
- a thread control that inactivates a first one of the N hardware threads in the register file and activates a second one of the N hardware threads in the register file and, in response to the inactivation of the first one of the N hardware threads and the activation of the second one of the N hardware threads, unloads register values associated with a first architected state of the processor system from the inactivated thread to registers of one of the M hardware threads and loads register values from one of the M hardware threads associated with a second architected state of the processor system to the inactivated thread in the register file;
- wherein the thread control aligns the one of the N hardware threads in the register file with the one of the M hardware threads in the offline storage structure to form a shift register ring for unloading the register values associated with the first architected state and loading of the register values associated with the second architected state concurrently.
2 more elements
Dependencies are inferred from the claim text.