US 7,600,099 B2 · System and method for predictive early allocation of stores in a microprocessor

Abstract

A system and method for predictive early allocation of stores in a microprocessor is presented. During instruction dispatch, an instruction dispatch unit retrieves an instruction from an instruction cache (Icache). When the retrieved instruction is an interruptible instruction, the instruction dispatch unit loads the interruptible instruction's instruction tag (IITAG) into an interruptible instruction tag register. A load store unit loads subsequent instruction information (instruction tag and store data) along with the interruptible instruction tag in a store data queue entry. Comparison logic receives a completing instruction tag from completion logic, and compares the completing instruction tag with the interruptible instruction tags included in the store data queue entries. In turn, deallocation logic deallocates those store data queue entries that include an interruptible instruction tag that matches the completing instruction tag.

Claims14

Dependent claims

A computer-implemented method comprising:

selecting a first instruction that is completing an execution process, wherein the first instruction is a first interruptible instruction and is selected from the group consisting of a branch instruction and a trap instruction;
identifying a completing instruction tag corresponding to the first instruction;
selecting a store data queue entry that is stored in a store data queue and includes an interruptible instruction tag, wherein the store data queue entry corresponds to a second instruction, which is a store instruction, and is subsequent in code to the first instruction and is dependent upon a result of the completion of the first instruction;
comparing the completing instruction tag with the interruptible instruction tag;
and
in response to the comparing, deallocating the store data queue entry based upon the completing instruction tag matching the interruptible instruction tag.

3 more elements

A computer program product stored on computer memory, the computer memory containing instructions for execution by a computer, which, when executed by the computer, cause the computer to implement a method to deallocate one or more store data queue entries, the method comprising:

selecting a first instruction that is completing an execution process, wherein the first instruction is a first interruptible instruction and is selected from the group consisting of a branch instruction and a trap instruction;
identifying a completing instruction tag corresponding to the first instruction;
selecting a store data queue entry that is stored in a store data queue and includes an interruptible instruction tag, wherein the store data queue entry corresponds to a second instruction, which is a store instruction, and is subsequent in code to the first instruction and is dependent upon a result of the completion of the first instruction;
comparing the completing instruction tag with the interruptible instruction tag;
and in response to the comparing, deallocating the store data queue entry based upon the completing instruction tag matching the interruptible instruction tag.

2 more elements

An information handling system comprising:

one or more processors;
a memory accessible by the processors;
one or more nonvolatile storage devices accessible by the processors;
and
a set of instructions stored in the memory, wherein one or more of the processors executes the set of instructions in order to perform actions of:
selecting a first instruction that is completing an execution process, wherein the first instruction is a first interruptible instruction and is selected from the group consisting of a branch instruction and a trap instruction identifying a completing instruction tag corresponding to the first instruction;
selecting a store data queue entry that is stored in a store data queue and includes an interruptible instruction tag, wherein the store data queue entry corresponds to a second instruction, which is a store instruction, and is subsequent in code to the first instruction and is dependent upon a result of the completion of the first instruction;
comparing the completing instruction tag with the interruptible instruction tag;
and
in response to the comparing, deallocating the store data queue entry based upon the completing instruction tag matching the interruptible instruction tag.

7 more elements

Dependencies are inferred from the claim text.

System and method for predictive early allocation of stores in a microprocessor

Life of this patent

System and method for predictive early allocation of stores in a microprocessor

Life of this patent

Abstract

Claims14