Method and system for efficient implementation of very large store buffer
AssigneeSun Microsystems, Inc.
InventorYuan C. Chou
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Abstract
A method and system for efficient implementation of a large store buffer within a processor includes a store buffer within a processor having a first component configured to hold a plurality of younger stores requested by the processor and a second component configured to hold a plurality of older stores. The first component is implemented as a small content addressable memory (CAM) and the second component includes a first-in-first-out (FIFO) buffer to hold the data and addresses of the plurality of older stores and an address disambiguator to hold the addresses of each of the plurality of older stores found in the FIFO buffer. The processor uses the small CAM to perform most of the store-to-load forwarding in a fast and efficient way thereby enhancing processor performance.
Claims11
A system for efficient implementation of a large store buffer within a processor of a computing system, comprising:
- a first component in the store buffer configured to hold one or more addresses and data corresponding to each of a plurality of stores, the plurality of stores in the first component include younger stores requested by the processor, the first component capable of handling store-to-load forwarding;
- and
- a second component within the store buffer communicatively linked to the first component, the second component configured to hold one or more addresses and data corresponding to each of a plurality of older stores, each of the plurality of older stores having been moved from the first component, wherein the second component further includes:
- a first-in-first-out (FIFO) buffer configured to hold one or more addresses and data corresponding to each of the plurality of older stores in program order;
- and
- an address disambiguator configured to hold one or more of the addresses corresponding to each of the plurality of older stores stored in the FIFO buffer, the address disambiguator providing store-to-load alias detection for one or more of the plurality of older stores stored in the FIFO buffer for store conflict resolutions,
- wherein the address disambiguator further comprising a counter to keep track of a number of stores in the FIFO buffer with addresses that fall within a range of addresses represented by disambiguator entries, the counter adjusted based on addition or removal of stores from the FIFO buffer that fall within a corresponding address range.
A method for efficient implementation of a large store buffer-queue with in a processor of a computing system, comprising:
- executing a load instruction in the processor, the load instruction including address associated with data;
- searching for an address match with an older store in a store buffer within the processor and for an address match in a data cache, the store buffer having a first component configured to hold one or more addresses and data corresponding to each of a plurality of younger stores requested by the processor and performing store-to-load forwarding and a second component configured to hold one or more addresses and data corresponding to each of a plurality of older stores, each of the plurality of older stores having been moved from the first component, the second component of the store buffer further including a first-in-first-out (FIFO) buffer configured to hold one or more addresses and data corresponding to each of the plurality of older stores in program order and an address disambiguator configured to hold one or more addresses corresponding to each of the plurality of older stores in the FIFO buffer, the address disambiguator providing store-to-load alias detection for one or more older stores stored in the FIFO buffer,
- wherein searching for an address match further includes,
- searching the address disambiguator of the second component for an address match;
- upon an address match in the address disambiguator, deferring execution of the load instruction upon a no-match of address for a store older than the load instruction in the first component of the store buffer;
- and
- providing the data requested by the load instruction from the store buffer or data cache upon an address match.
Dependencies are inferred from the claim text.