Detecting raw hazards in an object-addressed memory hierarchy by comparing an object identifier and offset for a load instruction to object identifiers and offsets in a store queue

An apparatus that efficiently processes memory-access instructions in an object-addressed memory hierarchy, comprising:

• an instruction-processing mechanism configured to receive a load instruction to be executed, wherein the load instruction loads a data item from an object, and wherein the load instruction specifies an object identifier (OID) for the object and an offset for the data item within the object;
• wherein the instruction-processing mechanism is further configured to receive at least one store instruction to be executed, wherein the store instruction specifies an OID and an offset, and wherein the instruction-processing mechanism is further configured to:
• create an entry in a store queue for the store instruction, wherein the entry includes a valid flag for the offset for the store instruction and a separate valid flag for the OID for the store instruction;
• when the offset for the store instruction becomes available, store the offset for the store instruction into the entry and set the valid flag for the offset for the store instruction;
• when the OID for the store instruction becomes available, store the OID for the store instruction into the entry and set the valid flag for the OID for the store instruction;
• and
• when a data value for the store instruction becomes available, store the data value into a data field of the entry;
• a comparison mechanism configured to compare the OID and the offset for the load instruction against OIDs and offsets for outstanding store instructions in the store queue;
• and
• wherein if the offset for the load instruction does not match any of the offsets for the outstanding store instructions in the store queue, and hence no RAW hazard exists, the instruction-processing mechanism is configured to perform a cache access to retrieve the data item for the load instruction.

A computer system which is configured to efficiently processes memory-access instructions in an object-addressed memory hierarchy, comprising:

• a processor;
• a memory;
• an instruction-processing mechanism within the processor configured to receive a load instruction to be executed, wherein the load instruction loads a data item from an object, and wherein the load instruction specifies an object identifier (OID) for the object and an offset for the data item within the object;
• wherein the instruction-processing mechanism is further configured to receive at least one store instruction to be executed, wherein the store instruction specifies an OID and an offset, and wherein the instruction-processing mechanism is further configured to:
• create an entry in a store queue for the store instruction, wherein the entry includes a valid flag for the offset for the store instruction and a separate valid flag for the OID for the store instruction;
• when the offset for the store instruction becomes available, store the offset into the entry and set the valid flag for the offset for the store instruction;
• when the OID for the store instruction becomes available, store the OID for the store instruction into the entry and set the valid flag for the OID for the store instruction;
• and
• when a data value for the store instruction becomes available, store the data value into a data field of the entry;
• a comparison mechanism within the processor configured to compare the OID and the offset for the load instruction against OIDs and offsets for outstanding store instructions in the store queue;
• and
• wherein if the offset for the load instruction does not match any of the offsets for the outstanding store instructions in the store queue, and hence no RAW hazard exists, the instruction-processing mechanism is configured to perform a cache access to retrieve the data item for the load instruction.