Back to results
US 7,600,084 B1Granted
Register file with integrated routing to execution units for multi-threaded processors
AssigneeMarvell International Ltd.
InventorsDennis M. O'Connor, Lawrence T. Clark
Life of this patent
Estimating the term…
Abstract
A multi-context register file for use in a multi-threaded processor includes at least one multi-context register file cell having internal routing functionality.
Claims26
A multi-context register file comprising:
- a first register file cell including:
- a plurality of storage cells to store data corresponding to a plurality of processing threads, the plurality of storage cells including:
- a first storage cell to store a portion of a first operand of an instruction of a first processing thread;
- and
- a second storage cell to store a portion of a second operand of an instruction of a second processing thread;
- and
- wherein the first register file cell further includes a first router in communication with the plurality of storage cells to couple a selected storage cell of the first register file cell to an input of a selected functional unit in response to control information.
4 more elements
A microprocessor comprising:
- a plurality of functional units to perform predetermined processing functions, each functional unit including one or more inputs to receive operands;
- and
- a multi-context register file having a plurality of register file cells, the plurality of register file cells including a first register file cell, the first register file cell comprising:
- a plurality of storage cells to store data corresponding to a plurality of processing threads, the plurality of storage cells including:
- a first storage cell to store a portion of a first operand of an instruction of a first processing thread;
- and
- a second storage cell to store a portion of a second operand of an instruction of a second processing thread;
- and
- wherein the first register file cell further includes a first router in communication with the plurality of storage cells and the plurality of functional units to couple a selected storage cell of the first register file cell to an input of a selected functional unit in response to control information.
6 more elements
A computer comprising:
- a microprocessor;
- and
- a flash memory in communication with the microprocessor to perform data storage functions in association therewith;
- wherein the microprocessor includes:
- a plurality of functional units to perform predetermined processing functions, each functional unit including one or more inputs to receive operands;
- and
- a multi-context register file having a plurality of register file cells, the plurality of register file cells including a first register file cell, the first register file cell comprising:
- a plurality of storage cells to store data corresponding to a plurality of processing threads, the plurality of storage cells including a first storage cell to store a portion of a first operand of an instruction of a first processing thread and a second storage cell to store a portion of a second operand of an instruction of a second processing thread;
- and
- a router in communication with the plurality of storage cells and the plurality of functional units to couple a selected storage cell of the first register file cell to an input of a selected functional unit in response to control information.
7 more elements
A method comprising:
- storing respective portions of operands of respective instructions of a plurality of processing threads within respective storage cells of a first register file cell;
- determining that a portion of a first operand of an instruction of a first processing thread is to be delivered from the first register file cell to an input of a first functional unit of a plurality of functional units;
- and
- routing the portion of the first operand to the input of the first functional unit using a first router within the first register file cell.
1 more element
Dependencies are inferred from the claim text.