Processor architecture having multi-ported memory

A data processing system comprising:

• a multiport memory module having first ports, M second ports, and J third ports, wherein N and M are integers greater than or equal to one and J is an integer greater than one;
• first data communication buses and M second data communication buses;
• N hardware acceleration modules that communicate with a respective one of the N first ports on a respective one of the N first data communication buses;
• M programmable sideband processor modules that communicate with a respective one of the M second ports on a respective one of the M second data communication buses,
• wherein one of the N hardware acceleration modules performs a first processing task on data and transmits the data to the multiport memory module on one of the N first data communication buses and one of the M programmable sideband processor modules receives the data from the multiport memory module on one of the M second data communication buses and performs a second processing task on the data, wherein the N hardware acceleration modules store intermediate data in the multiport memory module while performing processing tasks, and wherein N and N are integers greater than or equal to one;
• and
• a shared bus that includes a first bus portion that communicates with the N hardware acceleration modules and the M programmable sideband processor modules at a first rate, a second bus portion that communicates with J-A processor modules and J-B RAM modules at a second rate, and a bus bridge that communicates with the first bus portion and the second bus portion, wherein A and B are integers greater than or equal to one, and A+B=J.

A data processing system comprising:

• multiport memory means for storing data and having N first ports and J second ports, wherein N and J are integers greater than one;
• N first data communication bus means for transmitting data and J second data communication bus means for transmitting data;
• N hardware acceleration means for communicating with a respective one of the N first ports on a respective one of the N first data communication bus means,
• wherein a first one of the N hardware acceleration means performs a first processing task on data and transmits the data to the multiport memory means on a first one of the N first data communication bus means, a second one of the N hardware acceleration means receives the data from the multiport memory means on a second one of the N first data communication buses and performs a second processing task on the data, wherein the N hardware acceleration means store intermediate data in the multiport memory means while performing processing tasks;
• J-A processor means and J-B dynamic random access memory (DRAM) means for communicating with the multiport memory means on respective ones of the J second data communication bus means, wherein A and B are integers greater than or equal to one, and A+B=J;
• and
• a shared bus, comprising:
• first bus portion means for communicating with the N hardware acceleration means at a first rate;
• second bus portion means for communicating with the J-A processor means and the J-B DRAM means at a second rate;
• and
• bus bridge means for communicating with the first bus portion means and the second bus portion means.

A data processing method comprising:

• performing a first processing task on data at a first one of N hardware acceleration modules, wherein N is an integer greater than one;
• transmitting the data to a respective first one of N ports of a multiport memory module on a respective first one of N data communication buses;
• receiving the data from a respective second one of the N ports of the multiport memory module at a second one of the N hardware acceleration modules on a respective second one of the N data communication buses;
• performing a second processing task on the data at the second one of the N hardware acceleration modules,
• wherein the N hardware acceleration modules store intermediate data in the multiport memory module while performing processing tasks;
• communicating with J-A processor modules and J-B dynamic random access memory (DRAM) modules with the multiport memory module on respective ones of J additional data communication buses, wherein J is an integer greater than one, A and B are integers greater than or equal to one, and A+B=J;
• communicating on a first bus portion of a shared bus at a first rate with the N hardware acceleration modules;
• communicating on a second bus portion of the shared bus at a second rate with the J-A processor modules and the J-B DRAN modules;
• and
• communicating with the first bus portion and the second bus portion with a bus bridge.