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US 7,600,080 B1Granted
Avoiding deadlocks in a multiprocessor system
AssigneeIntel Corporation
InventorsBinata Bhattacharyya, Chandra P. Joshi, Chung-Chi Wang, Liang Yin, Vivek Garg, Phanindra K. Mannava
Life of this patent
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Abstract
In one embodiment, the present invention includes a method for receiving a first memory request from a first caching agent associated with a first processor, in a home agent associated with a memory, directing the first memory request to a writeback queue of the home agent if the first memory request is a writeback request and otherwise directing the first memory request to a second queue of the home agent. In this way, circular dependencies may be avoided. Other embodiments are described and claimed.
Claims14
A method comprising:
- receiving, in a home agent via a router, a first memory request from a first caching agent associated with a first processor socket if the first memory request is directed to a location within the first processor socket and otherwise passing the first memory request to a second processor socket from the router;
- directing the first memory request to a writeback queue of the home agent if the first memory request is a writeback request, the writeback queue to store only writeback transactions;
- directing the first memory request to a second queue of the home agent if the first memory request is not a writeback request;
- sending the writeback request from the writeback queue to a memory;
- receiving, in the home agent from the memory, an acknowledgment message indicating completion of the writeback request;
- deallocating the writeback request from the writeback queue of the home agent;
- sending an acknowledgment message indicating completion of the first memory request from the home agent to the first caching agent;
- and
- deallocating the first memory request from a tracker of the first caching agent responsive to the acknowledgment message, wherein only a single message per address is to be allocated into the tracker.
6 more elements
An apparatus comprising:
- a first processor socket including a first core, a first cache memory, a first caching agent, a router to couple to the first caching agent to a home agent and to a second router of a second processor socket, the router to direct memory requests from the first caching agent to the home agent if directed to a location within the first processor socket and otherwise to the second router, the home agent including a first storage to store memory requests from the first caching agent and a second caching agent of the second processor socket and a second storage to store only writeback requests from the first caching agent and the second caching agent, wherein the home agent is to direct a writeback request from the first caching agent into the second storage, deallocate the writeback request from the second storage after receipt of an acknowledgment message indicative of completion of the writeback request in a memory coupled to the home agent, and the first caching agent is to deallocate the writeback request from a tracker of the first caching agent responsive to an acknowledgment message indicative of the deallocation from the second storage.
A system comprising:
- a first processor socket having a first processing unit, a first memory, a first caching agent, and a home agent including a first queue to store memory requests and a second queue to store only writeback requests, wherein the home agent is to receive a writeback request from the first caching agent and direct the writeback request into the second queue and to deallocate the writeback request from the second queue after completion of a writeback and send an acknowledgement of the completion to the first caching agent, which in turn is to deallocate the writeback request from a tracker of the first caching agent;
- a second processor socket coupled to the first processor socket having a second processing unit, a second memory, and a second caching agent;
- and
- a dynamic random access memory (DRAM) coupled to the first processor socket.
1 more element
Dependencies are inferred from the claim text.