An apparatus for performing a cacheline polling operation within an information handling system, said apparatus comprising:
- a memory comprising a first cacheable memory location which includes a plurality of cacheable memory locations;
- and
- a processing element coupled to said memory, said processor comprising:
- means for storing a buffer flag busy indicator data value within a first cacheable memory location within said memory and for setting a load/store operation reservation associated with said first cacheable memory location via execution of a store and reserve (STAR) instruction, such that said storing of said buffer flag busy indicator value via said execution of said STAR instruction signals an external device having access to said memory that said data has been stored within said memory and may be accessed by said external device;
- means for executing a load when reservation lost (LDRL) instruction to determine whether said load/store operation reservation has been reset corresponding to a modification of data within said first cacheable memory location by said external device;
- means for comparing a present data value stored within said first cacheable memory location to said buffer flag busy indicator data value in response to an access by said external device to said first cacheable memory location;
- and
- means for stalling execution of said LDRL instruction until a determination that said load/store operation reservation associated with said first cacheable memory location has been reset with a “not busy” indicator data value being stored in said first cacheable memory location by said external device.