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US 7,600,071 B2Granted
Circuit having relaxed setup time via reciprocal clock and data gating
AssigneeInternational Business Machines Corporation
InventorEd Seewann
Life of this patent
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Abstract
An integrated circuit includes a circuit output, a data input that receives a data signal, and a clock input that receives a clock signal. The integrated circuit further includes first and second logic gates. The first logic gate has a first input coupled to the clock input, a second input coupled to the data input, and an output and a second logic gate. The second logic gate has a first input coupled to the data input, a second input coupled to the output of the first logic gate, and an output coupled to the circuit output. Setup time of the data signal relative to the clock signal at the second logic gate is improved by reciprocal gating of the data and clock signals.
Claims20
An integrated circuit, comprising:
- a circuit output;
- a data input that receives a data signal;
- a clock input that receives a clock signal;
- a first logic gate having a first input coupled to the clock input, a second input coupled to the data input, and an output;
- and
- a second logic gate having a first input coupled to the data input, a second input coupled to the output of the first logic gate, and an output coupled to the circuit output, wherein a setup time of the data signal relative to the clock signal at said second logic gate is improved by reciprocal gating of the data and clock signals.
3 more elements
A memory circuit, comprising:
- a plurality of memory cells that generate a plurality of matchline signals;
- and
- a plurality of wordline driver circuits each coupled to receive a respective one of the matchline signals, wherein each of the plurality of wordline driver circuits includes:
- a circuit output;
- a data input that receives a matchline signal among the plurality of matchline signals;
- a clock input that receives a clock signal;
- a first logic gate having a first input coupled to the clock input, a second input coupled to the data input, and an output;
- and
- a second logic gate having a first input coupled to the data input, a second input coupled to the output of the first logic gate, and an output coupled to the circuit output, wherein a setup time of the matchline signal relative to the clock signal at said second logic gate is improved by reciprocal gating of the matchline and clock signals.
6 more elements
A processor comprising:
- a cache memory that employs real addresses;
- a plurality of execution units for executing instructions;
- an instruction sequencing unit that fetches instructions from the cache memory for execution by the execution units;
- and
- a circuit within the processor including:
- a circuit output;
- a data input that receives a data signal;
- a clock input that receives a clock signal;
- a first logic gate having a first input coupled to the clock input, a second input coupled to the data input, and an output;
- and
- a second logic gate having a first input coupled to the data input, a second input coupled to the output of the first logic gate, and an output coupled to the circuit output, wherein a setup time of the data signal relative to the clock signal at said second logic gate is improved by reciprocal gating of the data and clock signals.
8 more elements
A processor comprising:
- a cache memory that employs real addresses;
- a plurality of execution units for executing instructions;
- an instruction sequencing unit that fetches instructions from the cache memory for execution by the execution units;
- and
- an effective-to-real address translation table that translates effective addresses to real addresses to permit access to the cache memory, the effective-to-real address translation table including:
- a plurality of content addressable memory cells for storing effective addresses, wherein said plurality of content addressable memory cells generates a plurality of matchline signals in response to an input effective address;
- a plurality of wordline driver circuits each coupled to receive a respective one of the matchline signals, wherein each of the plurality of wordline driver circuits includes:
- a circuit output;
- a data input that receives a matchline signal among the plurality of matchline signals;
- a clock input that receives a clock signal;
- a first logic gate having a first input coupled to the clock input, a second input coupled to the data input, and an output;
- and
- a second logic gate having a first input coupled to the data input, a second input coupled to the output of the first logic gate, and an output coupled to the circuit output, wherein a setup time of the matchline signal relative to the clock signal at said second logic gate is improved by reciprocal gating of the matchline and clock signals;
- and
- a random access memory having a plurality of entries corresponding in number to said plurality of content addressable memory cells, wherein each entry of said plurality of entries includes a wordline that is asserted to read out a real address stored in that entry, and wherein each of the wordlines is coupled to the circuit output of a respective one of the plurality of wordline driver circuits.
12 more elements
Dependencies are inferred from the claim text.