Programmable control interface device
AssigneeSTMicroelectronics S.r.l.
InventorsHerve Chalopin, Laurent Tabaries
Life of this patent
Estimating the term…
Abstract
A programmable control interface is for circuits using complex commands. The programmable interface includes a memory for storing sampled commands and a sequencing circuit. The sequencing circuit is programmable. Thus, a processor downloads into the programmable interface a sequencing specific to the sequence of commands. Once the programmable interface has been programmed, the processor launches the start of the sequence and the programmable interface manages and controls in a standalone manner the inputs/outputs with the slave circuit. The management and control of the slave circuit is independent of any interrupt specific to the system. The programmable interface uses a software-type upgrade to interface with new slave circuits that may appear on the market.
Claims20
A programmable interface device for controlling a slave circuit, wherein any control signal intended to control the slave circuit is previously decomposed into a succession of bits, the succession corresponding to a sampling of the signal with the aid of a sampling signal, a period of which is at most equal to the smallest duration between two changes of state of the control signal, said device comprising:
- a first memory for storing sampled commands of the sampled control signal;
- a first address counter for supplying addresses to said first memory;
- and
- a programmable state machine for driving the first memory and the first address counter, the state machine including:
- a state memory structured to store first address counter control bits for controlling the first address counter and first memory control bits for controlling the first memory;
- and
- a state memory controller structured to cause the state memory to output the first address counter control bits and first memory control bits, and thereby cause the first memory to be controlled in response to the first memory control bits and cause the first address counter to be controlled in response to the first address counter control bits.
An electronic system comprising:
- a central processor furnished with a central bus for exchanging data, addresses and commands with other circuits;
- a command bank memory storing at least one set of complex instructions corresponding to at least one slave circuit, the memory being coupled to the central bus;
- and
- a programmable interface device coupled to the central bus for controlling the at least one slave circuit, the interface device including:
- a first memory for storing the complex instructions;
- a first address counter for supplying addresses to said first memory;
- and
- a programmable state machine for driving the first memory and the first address counter, the state machine including:
- a state memory structured to store first address counter control bits for controlling the first address counter and first memory control bits for controlling the first memory;
- and
- a state memory controller structured to cause the state memory to output the first address counter control bits and first memory control bits, and thereby cause the first memory to be controlled in response to the first memory control bits and cause the first address counter to be controlled in response to the first address counter control bits.
A method, comprising:
- controlling a slave circuit using a control signal, wherein the controlling includes:
- computing a series of sampled commands by decomposing the control signal into a succession of bits by sampling using a sampling signal having a period that is at most equal to a smallest duration between two changes of state of the control signal;
- loading the sampled commands into a first memory;
- loading, into a state memory of a state machine, address counter control bits for controlling a first address counter and first memory control bits for controlling the first memory;
- and
- after the loading steps, causing the address counter to address the first memory by supplying from the state machine to the address counter the address counter control bits, and supplying from the state machine to the first memory instructions for causing the first memory to provide on an output bus signals intended for commanding the slave circuit.
Dependencies are inferred from the claim text.