Efficient hardware divide operation

An apparatus that uses the Newton-Raphson technique to perform a division operation, comprising:

• a receiving mechanism configured to receive a numerator a and a denominator b;
• and
• a division mechanism configured to divide a by b by first using the Newton-Raphson technique to find 1/b, and then multiplying 1/b by a to produce the result a/b;
• wherein while using the Newton-Raphson technique to find 1/b, the division mechanism is configured to obtain an initial estimate x0 for 1/b and to iteratively solve the equation xi+1=xi(2−bxi);
• wherein while iteratively solving the equation xi+1=xi(2−bxi), the division mechanism is configured to,
• use a multiplier circuit to multiply b by xi to compute bxi,
• perform a bit-wise complement operation on bxi to compute 2−bxi, whereby an additional pass through an adder circuit or a multiply/add circuit is not required to perform the subtraction operation, and to
• use the multiplier circuit to multiply xi by 2−bxi to compute xi(2−bxi),
• wherein a separate inverter and a separate multiplexer are attached to each bit position of the multiplier circuit to selectively perform a bit-wise complement or a shift operation during specific passes through the multiplier circuit.