Efficient hardware square-root operation

An apparatus that uses the Newton-Raphson technique to compute a square-root, comprising:

• a receiving mechanism configured to receive a radicand b;
• and
• a square-root mechanism configured to calculate √{square root over (b)} by first using the Newton-Raphson technique to find 1/√{square root over (b)}, and then multiplying 1/√{square root over (b)} by b to produce √{square root over (b)};
• wherein while using the Newton-Raphson technique to find 1/√{square root over (b)}, the square-root mechanism is configured to obtain an initial estimate x0 for 1/√{square root over (b)}, and to iteratively solve the equation
• x
• i
• +
• 1
• =
• x
• i
• ⁡
• (
• 3
• -
• bx
• i
• 2
• 2
• )
• ;
• wherein while iterative solving the equation
• x
• i
• +
• 1
• =
• x
• i
• ⁡
• (
• 3
• -
• bx
• i
• 2
• 2
• )
• ,
• the square-root mechanism is configured to,
• use the multiplier circuit twice to compute bxi2,
• perform a bit-wise complement operation on bxi2, shift the result, and modify the first two bits of the result to compute
• 3
• -
• bx
• i
• 2
• 2
• ,
• whereby an additional pass through an adder circuit or a multiply/add circuit is not required to perform the subtraction operation, and to
• use the multiplier circuit to multiply xi by
• 3
• -
• bx
• i
• 2
• 2
• to compute
• x
• i
• ⁡
• (
• 3
• -
• bx
• i
• 2
• 2
• )
• ,
• wherein a separate inverter and a separate multiplexer are attached to each bit position of the multiplier circuit to selectively perform a bit-wise complement or a shift operation during specific passes through the multiplier circuit.