Apparatus for hybrid multiplier in GF(2m) and method thereof
AssigneeElectronics and Telecommunications Research Institute
InventorsYong Je Choi, Ku Young Chang, Do Won Hong, Hyun Sook Cho
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AssigneeElectronics and Telecommunications Research Institute
InventorsYong Je Choi, Ku Young Chang, Do Won Hong, Hyun Sook Cho
Estimating the term…
An apparatus and method for hybrid multiplication in GF(2m) by which trade-off between the area and the operation speed of an apparatus for a hybrid multiplier in finite field GF(2m) can be achieved are provided. The apparatus for hybrid multiplication includes: a matrix Z generation unit generating [m×k] matrix Z for performing a partial multiplication of a(x) and b(x), by dividing b(x) by k bits (k≦┌m/2┐), when multiplication of m-bit multiplier a(x) and m-bit multiplicand b(x) is performed from [(m+k−1)×k] coefficient matrix of a(x) in GF(2m); a partial multiplication unit performing the partial multiplication ┌m/k┐k−1 times in units of rows of the matrix Z to calculate an (┌m/k┐k−1)-th partial multiplication value and a final result value of the multiplication; and a reduction unit receiving the (┌m/k┐k−1)-th partial multiplication value fed back from the partial multiplication unit and performing reduction of the value in order to obtain a partial multiplication value next to the (┌m/k┐k−1)-th partial multiplication value.
An apparatus for hybrid multiplication comprising:
Dependencies are inferred from the claim text.