US 7,599,974 B2Granted

Data processing apparatus and method for comparing floating point operands

AssigneeArm Limited

InventorsChristopher Neal Hinds, David Raymond Lutz

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Abstract

A data processing apparatus compares first and second floating point operands to produce a comparison result. For each floating point operand, a first component is derived from a predetermined number of MSBs of the fraction component which is less than the total number of bits constituting the fraction component. The sign and exponent components of the first and second floating point operands are compared to produce a plurality of signals. If possible, the comparison result is determined from the plurality of signals. For each floating point operand, a second component is derived from the bits of the fraction component of that floating point operand other than the predetermined number of MSBs. The second components of the first and second floating point operands to are compared produce a further signal. The comparison result is determined from the plurality of signals and the further signal.

Claims28

Dependent claims

A data processing apparatus for comparing first and second floating point operands to produce a comparison result, each first and second floating point operand having a sign component, an exponent component and a fraction component, the data processing apparatus comprising:

first processing logic circuitry configured to receive, for each floating point operand, a first component derived from a predetermined number of most significant bits of the fraction component of that floating point operand, said predetermined number being less than the total number of bits constituting the fraction component, the first processing logic circuitry being further configured to receive the sign components and the exponent components of the first and second floating point operands, to compare the sign components, the exponent components and the first components of the first and second floating point operands, and to produce a plurality of signals indicative of the comparison;
evaluation logic circuitry configured to evaluate whether the comparison result is determinable from the plurality of signals, and if so, to determine the comparison result;
second processing logic circuitry configured, in the event that the evaluation logic circuitry determines that the comparison result is not determinable from the plurality of signals, to receive, for each floating point operand, a second component derived from at least the bits of the fraction component of that floating point operand other than said predetermined number of most significant bits, and to compare the second components of the first and second floating point operands in order to produce at least one further signal indicative of said comparison;
and
the evaluation logic circuitry being further configured to determine the comparison result from said plurality of signals and said at least one further signal.

2 more elements

A method of operating a data processing apparatus to compare first and second floating point operands to produce a comparison result, each first and second floating point operand having a sign component, an exponent component and a fraction component, the method comprising the steps of:

(a) receiving at first processing logic circuitry, for each floating point operand, a first component derived from a predetermined number of most significant bits of the fraction component of that floating point operand, said predetermined number being less than the total number of bits constituting the fraction component, the first processing logic circuitry also receiving the sign components and the exponent components of the first and second floating point operands;
(b) employing the first processing logic circuitry to compare the sign components, the exponent components and the first components of the first and second floating point operands, and to produce a plurality of signals indicative of the comparison;
(c) evaluating whether the comparison result is determinable from the plurality of signals, and if so, determining the comparison result;
(d) in the event that at said step (c) it is determined that the comparison result is not determinable from the plurality of signals, receiving at second processing logic circuitry, for each floating point operand, a second component derived from at least the bits of the fraction component of that floating point operand other than said predetermined number of most significant bits;
(e) employing the second processing logic circuitry to compare the second components of the first and second floating point operands in order to produce at least one further signal indicative of said comparison;
and
(f) determining the comparison result from said plurality of signals produced at said step (b) and said at least one further signal produced at said step (e).

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/805,502Filed 22 Mar 2004
Published: US 2005/0210093 A122 Sep 2005
Granted: 6 Oct 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

G06F 7/026
Comparing digital values: magnitude comparison, i.e. determining the relative order of operands based on their numerical value, e.g. window comparator
G06F 7/483
Using non-contact-making devices, e.g. tube, solid state device; using unspecified devices: computations with numbers represented by a non-linear…
G06F
Computing and data processing