Hybrid analog/digital phase-lock loop with high-level event synchronization

A method of providing a low-jitter clock signal synchronized to a timing reference having jitter, said method comprising:

• generating a clock output from a numerically-controlled analog oscillator ratiometrically locked to a stable clock source, wherein a frequency of said clock output is controlled by a rational numeric representation of a ratio between a frequency of said clock output and a frequency of said stable clock;
• dividing a frequency of one of said clock output or said stable clock;
• generating a representation of an on-going phase-frequency difference between said timing reference and a result of said dividing;
• filtering said representation of said on-going phase-frequency difference with a digital filter to provide said rational numeric representation to said numerically-controlled analog oscillator;
• receiving a synchronization event signal;
• and
• resetting an accumulated phase error of said digital phase-frequency detector in response to receiving said synchronization event signal.

A circuit for providing a low-jitter clock output synchronized to a timing reference having jitter, said circuit comprising:

• a numerically-controlled analog oscillator for providing said clock output and having an input for receiving a rational numeric representation of a ratio between a frequency of said clock output and a frequency of a stable clock for controlling said frequency of said clock output;
• a counter for dividing a frequency of one of said clock output or said stable clock;
• a digital phase-frequency detector for generating a representation of an on-going phase-frequency difference between said timing reference and an output of said counter;
• a digital loop filter for filtering said representation of said on-going phase-frequency difference to provide said rational numeric representation to said numerically-controlled analog oscillator;
• and
• means for resetting an accumulated phase error of said digital phase-frequency detector in response to a synchronization event.