Method and apparatus for generating one or more clock signals for a decision-feedback equalizer using DFE detected data in the presence of an adverse pattern

A receiver employing decision-feedback equalization, comprising:

• a plurality of switches configured to sample a received signal using a data clock and a transition clock to generate a data sample signal and a transition sample signal;
• at least one decision-feedback equalization (DFE) block configured to generate a DFE correction for each of said data sample and transition sample signals to generate DFE detected data and a DFE transition data;
• a phase detector configured to generate a phase update of one or more of said data clock and said transition clock based on said DFE detected data and said DFE transition data;
• and
• a pattern detector configured to enable a modification of one or more of said phase updates if said DFE detected data satisfies one or more predefined conditions.

A receiver employing decision-feedback equalization, comprising:

• a plurality of switches configured to sample a received signal using a data clock and a transition clock to generate a data sample signal and a transition sample signal;
• at least one decision-feedback equalization (DFE) block configured to generate a plurality of precomputed DFE corrections for each of said data sample and transition sample signals;
• DFE logic configured to select one of said precomputed DFE corrections to generate said DFE detected data and said DFE transition data;
• a phase detector configured to generate a phase update of one or more of said data clock and said transition clock based on said DFE detected data and said DFE transition data;
• and
• a pattern detector configured to enable a modification of one or more of said phase updates if said DFE detected data satisfies one or more predefined conditions.