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US 7,599,458 B2Granted
System and method to reduce jitter
AssigneeHewlett-Packard Development Company, L.P.
InventorsSamuel D. Naffziger, Steven F. Liepe
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Abstract
One disclosed embodiment may comprise an interpolation system that includes an interpolator that interpolates between a selected phase from a preceding cycle and a selected phase from a current cycle to provide an interpolated phase for the current cycle. An edge of the interpolated phase for the current cycle has reduced jitter relative to an edge of a corresponding phase of the current cycle. A delay system delays a plurality of other phases of the current cycle to provide delayed other phases, the delayed other phases and the interpolated phase for the current cycle collectively defining a set of adjusted phases for the current cycle.
Claims30
An interpolation system comprising:
- an interpolator that phase interpolates between a selected phase from an adjacent preceding clock cycle and a selected phase from a current clock cycle to provide an interpolated phase for the current clock cycle, wherein the interpolated phase for the current clock cycle has reduced jitter relative to a corresponding phase of the preceding clock cycle;
- and
- a delay system that delays the selected phase from the current clock cycle to correspond with the selected phase of the preceding clock cycle, the delay system further delaying a plurality of other phases of the current clock cycle to provide delayed other phases, where the amount of delay of the other phases is configured to substantially match an amount of delay associated with the interpolation, the delayed other phases and the interpolated phase for the current clock cycle collectively defining a set of adjusted phases for the current clock cycle.
A system comprising:
- a delay locked loop that provides a multi-phase signal based on a reference clock signal;
- and
- an interpolation system, comprising:
- an interpolator that phase interpolates the multi-phase signal of a selected phase of the multi-phase signal from an adjacent preceding cycle and an edge of a selected phase of the multi-phase signal from the current cycle to provide an interpolated first phase of the current cycle of the multi-phase signal;
- and
- a delay system that delays the selected phase from the current clock cycle to correspond with the selected phase of the preceding clock cycle, the delay system further delaying a plurality of phases of the multi-phase signal to provide a plurality of delayed phases of the multi-phase signal, where the amount of delay of the other phases is configured to substantially match an amount of delay associated with the interpolation, the plurality of delayed phases and the interpolated first phase of the current cycle collectively defining an adjusted multi-phase signal for the current cycle, the adjusted multi-phase signal for the current cycle having reduced jitter relative to the multi-phase signal provided by the delay locked loop.
3 more elements
A system comprising:
- means for phase interpolating the multi-phase signal between a selected phase from a an adjacent preceding cycle of a multi-phase signal and a phase from a current cycle of the multi-phase signal to provide an adjusted interpolated phase of the current cycle of the multi-phase signal;
- and
- means for delaying the selected phase from the current clock cycle to correspond with the selected phase of the preceding clock cycle, the means further delaying other phases of the multi-phase signal to provide a plurality of delayed phases for the current cycle of the multi-phase signal, where the amount of delay of the other phases is configured to substantially match an amount of delay associated with the interpolation, the plurality of delayed phases and the interpolated phase of the current cycle being combined to provide an adjusted multi-phase signal for the current cycle.
A method comprising:
- receiving a multi-phase signal having a plurality of phases, each of the plurality of phases having a respective edge that exhibits an amount of jitter;
- phase interpolating the multi-phase signal between a selected phase of an adjacent preceding cycle of the multi-phase signal and a selected phase of a current cycle to provide an interpolated edge that exhibits a reduced amount of jitter relative to the amount of jitter associated with the received multi-phase signal;
- delaying a selected phase from the current clock cycle to correspond with the selected phase of the preceding clock cycle;
- and
- delaying other phases of the multi-phase signal to provide a plurality of delayed phases for the current cycle of the multi-phase signal, where the amount of delay is configured to substantially match an amount of delay associated with the interpolation.
2 more elements
Dependencies are inferred from the claim text.