Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits

A clock-and-data recovery (CDR) system, comprising:

• a clock generator adapted to generate a plurality of phase-offset clock signals;
• and
• one or more channel circuits, each channel circuit adapted to generate an output data stream and a recovered clock signal based on an input data signal, wherein each channel circuit comprises:
• a data register for each phase-offset clock signal, the data register adapted to generate an output signal based on the level of the corresponding phase-offset clock signal at a transition in the input data signal;
• a logic circuit adapted to process the output signals from the data registers to select one of the phase-offset clock signals as a sampling clock signal;
• and
• a data sampler adapted to sample the input data signal based on the sampling clock signal to generate the output data stream and generate the recovered clock signal based on the sampling clock signal, wherein:
• each channel circuit comprises first and second banks of data registers;
• the CDR system is adapted to be selectively configured to operate in one of a first mode and a second mode;
• in the first mode, the CDR system is selectively configured such that:
• the clock generator generates a first set of phase-offset clock signals;
• the first set of phase-offset clock signals is applied to both the first and second banks of data registers;
• and
• the logic circuit selects a data register output signal corresponding to a phase-offset clock signal of the first set of phase-offset clock signals as the sampling clock signal;
• and
• in the second mode, the CDR system is selectively configured such that:
• the clock generator generates the first set of phase-offset clock signals and a second set of phase-offset clock signals;
• the first set of phase-offset clock signals is applied to the first bank of data registers;
• the second set of phase-offset clock signals is applied to the second bank of data registers;
• and
• the logic circuit selects a data register output signal corresponding to a phase-offset clock signal of the first and second sets of phase-offset clock signals as the sampling clock signal.