Bi-directional bridge circuit having high common mode rejection and high input sensitivity

A method for providing a bidirectional communications interface connecting a transmitter and a receiver to a transmission line, the method comprising:

• receiving differential pairs of signals from the transmission line and the transmitter;
• and
• generating an output logic signal to the receiver, including:
• (i) suppressing effects of input noise from a floating input on the output logic signal by skewing a transfer characteristic of an output amplifier characteristic using an asymmetric transfer characteristic that offsets signal levels of the output logic signals with regard to input noise;
• and
• (ii) controlling symmetry in switching transients of the output logic signal by increasing a logic threshold voltage of a logic gate of the output amplifier above a mid-supply voltage of the logic gate.

A computer program product stored on a tangible computer readable storage medium storing a plurality of executable instructions for execution by a processing system to perform a method of providing a bidirectional communications interface including a bridge connecting a transmitter and a receiver to a transmission line by:

• generating positive polarity data signals in a first differential amplifier and generating negative polarity data signals in a second differential amplifier, the first differential amplifier and second differential amplifier receiving differential signal pairs from each side of a differential link to the transmission line and the transmitter;
• independently controlling common mode rejection in each of the separate first and second differential amplifiers using bias signals generated in response to an output common mode feedback voltage from each of the first and second differential amplifiers;
• generating output logic signals representing data received on the transmission line from the positive polarity data signals and the negative polarity data signals;
• suppressing effects of input noise on the output logic signals by skewing an output amplifier transfer characteristic using an asymmetric transfer characteristic that offsets signal levels of the output logic signals with regard to input noise;
• and
• controlling symmetry in switching transients of the output logic signals by increasing a logic threshold voltage of a logic gate of the output amplifier above a mid-supply voltage of the logic gate.

A method for interfacing between a transmission line and a communication device, the method comprising:

• generating a positive polarity difference signal and a negative polarity difference signal by subtracting differential signals of the communication device from differential signals of the transmission line;
• generating a positive polarity data signal by differentially amplifying the positive polarity difference signal in a first differential amplifier;
• generating a negative polarity data signal by differentially amplifying the negative polarity difference signal in a second differential amplifier;
• generating an output logic signal representative of data received via the transmission line by differentially amplifying the positive polarity data signal and the negative polarity data signal;
• and
• the differentially amplifying suppresses input noise using an asymmetric transfer characteristic that offsets output signal logic levels with regard to input noise using an asymmetric transfer characteristic that offsets signal levels of the output logic signals with regard to input noise.

A method for providing high common mode rejection in a bidirectional bridge circuit that connects a transmitter and a receiver to a transmission line, the method comprising:

• providing separate first and second differential amplifiers for each side of a differential link to the transmission line and the transmitter;
• receiving first and second common mode output voltages from the first and second differential amplifiers;
• generating first and second common mode feedback voltages from the corresponding first and second common mode output voltages;
• and
• suppressing first and second common mode gains of the first and second differential amplifiers using the corresponding first and second common mode feedback voltages as bias control signals, wherein the common mode rejection of the differential amplifiers is increased,
• wherein the suppressing first and second common mode gains of the first and second differential amplifiers using the corresponding first and second common mode feedback voltages as bias control signals includes using an asymmetric transfer characteristic that offsets signal levels of output logic signals with regard to input noise.