Electronic communication control

An electronic communication line card for multiplex control comprising:

• a master control processor including:
• a storage module to store information;
• and
• a processing module to provide multiplexing control by matching senders with receivers, wherein the master control processor is disposed in a data path between a first network and a second network such that multiplexing control is performed prior to message data being processed by a host processor;
• a backplane interface configured to couple the line card to the host processor;
• an electronic communication interface configured to couple the line card to the first network and the second network;
• a first bus coupled to the master control processor, the backplane interface, and the electronic communication interface;
• a bus controller, configured to control bus communications, coupled to the first bus a second bus, and a third bus;
• an accelerator, including a configurable logic portion, coupled to the second bus and the third bus;
• and
• a storage module, coupled to the second bus.

An electronic communication control device comprising:

• a master control processor including:
• a storage module to store information;
• and
• a processing module configured to analyze network data traffic and to provide multiplexing control by blocking unwanted traffic, wherein the master control processor is disposed in a data path between a network and a host processor such that multiplexing control is performed prior to message data being processed by the host processor;
• a host interface configured to couple the electronic communication control device to the host processor;
• an electronic communication interface configured to couple the electronic communication control device to the network;
• and
• a first bus coupled to the master control processor, the host interface, and the communication device interface;
• a bus controller, configured to control bus communications, coupled to the first bus, a second bus, and a third bus, wherein the master control processor, the common data storage elements, the host interface, and the electronic communication device interface are each coupled to the second bus;
• an accelerator, including a configurable logic portion, coupled to the second bus and the third bus, wherein the accelerator is constructed to operate as a processor subordinate to the master processor;
• and
• a storage module, coupled to the second bus.