Semiconductor memory, memory controller and control method for semiconductor memory
AssigneeFujitsu Microelectronics Limited
InventorsSatoshi Eto, Kuninori Kawabata, Toshiya Miyo, Yuji Serizawa
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Abstract
A semiconductor memory for inputting and outputting data synchronously with a clock includes a clock reception unit for receiving the clock, and a command reception unit for initially receiving a first specific command synchronizing with the clock after turning a power on, after a low-power standby or after an initialization, followed by starting a command reception.
Claims19
Semiconductor memory for inputting and outputting data synchronously with a clock, comprising:
- a clock reception unit for receiving the clock;
- and
- a command reception unit for initially receiving a first specific command synchronizing with the clock after turning a power on, after a low-power standby or after an initialization, followed by starting a command reception,
- wherein the command reception unit receives a command at every N clocks after the first specific command is initially received,
- wherein N is an integer and greater than 1 (one), and
- wherein said command reception unit invalidates a command which is different from the first specific command and is received prior to initially receiving said first specific command.
A memory controller connected to semiconductor memory for inputting and outputting data synchronously with a clock, comprising:
- a clock reception unit for receiving the clock;
- and
- a command reception unit for initially receiving a first specific command synchronizing with the clock after turning a power on, after a low-power standby or after an initialization, followed by starting a command reception,
- wherein the command reception unit receives a command at every N clocks after the first specific command is initially received,
- wherein N is an integer and greater than 1 (one), and
- wherein said command reception unit invalidates a command which is different from the first specific command and is received prior to initially receiving said first specific command.
A control method used for semiconductor memory for inputting and outputting data synchronously with a clock, comprising:
- receiving the clock;
- invalidating a command which is different from a first specific command and is received prior to initially receiving said first specific command,
- initially receiving the first specific command synchronizing with the clock after turning a power on, after a low-power standby or after an initialization, followed by starting a command reception;
- and
- receiving a command at every N clocks after the first specific command is initially received,
- wherein N is an integer and greater than 1 (one).
Dependencies are inferred from the claim text.