Enhanced write abort mechanism for non-volatile memory

A method for carrying out a write-abort process to suspend attempts by a memory controller to write data into a non-volatile memory array of a memory device during low-voltage conditions, the method comprising:

• monitoring an output of a voltage supply powering the memory device with a voltage supervisor circuit;
• detecting a “low-voltage” condition of the voltage supply and, responsive thereto, asserting a “low-voltage” signal on a ready/busy signal line of the memory controller;
• subsequent to assertion of the “low-voltage” signal, completing any write cycle already started prior to assertion of the “low-voltage” condition signal using remaining power from the voltage supply;
• and
• suspending any unprocessed write commands while the “low-voltage” signal is asserted on the ready/busy signal line by causing the controller to treat the memory array as “busy” in response to assertion of the “low-voltage” signal on the ready/busy signal line of the memory controller and to continue treating the memory array as busy until the low-voltage signal is deasserted.

A method for carrying out a write-abort process to suspend attempts by a memory controller to write data into a non-volatile memory array during low-voltage conditions, the method comprising:

• monitoring an output of a voltage supply powering the non-volatile memory array;
• determining if a low-voltage condition exists at the output of the voltage supply;
• subsequent to determining that the low-voltage condition exits, completing any write cycle already started prior to detection of the low-voltage condition using remaining power from the voltage supply;
• and
• suspending any unprocessed write commands while the low-voltage condition exists.

A non-volatile memory apparatus, comprising:

• a non-volatile memory array;
• a voltage supervisor circuit configured for monitoring an output of a voltage supply powering the apparatus, the voltage supervisor circuit configured to assert a “low-voltage” signal responsive to detecting the output of the voltage supply dropping below a predetermined value;
• and
• a memory controller in communication with the memory array and configured to, subsequent to assertion of the “low-voltage” signal, complete any write cycle already started prior to assertion of the “low-voltage” signal using remaining power from the voltage supply and to suspend writing data for any subsequent write cycles while the “low-voltage” signal remains asserted.