Internal voltage generator of semiconductor memory device

A semiconductor memory device wherein after a minimum time for a bit line sense amplifier to amplify data passes from an input timing of a row address strobe command, a write/read operation is performed by an internal write/read command and then a precharge operation is performed by an internal precharge command, comprising:

• a plurality of voltage generators partitioned into two groups for generating an internal voltage;
• a first controller for enabling a first group of voltage generators for the minimum time and from an input timing of the internal write/read command to an input timing of the internal precharge command;
• and
• a second controller for enabling a second group of voltage generators and controlling the number of enabled voltage generators according to the level of the internal voltage from the end of the minimum time to the input timing of the internal write/read command.

A semiconductor memory device, comprising:

• a voltage sensor for detecting an internal voltage;
• a plurality of first control units for generating a plurality of internal control signals according to the voltage level of an output of the voltage sensor;
• and
• a plurality of voltage generators turned on/off in response to the plurality of internal control signals, wherein the each first control unit has its own logic threshold voltage.