Semiconductor memory device and driving method thereof

A semiconductor memory device, comprising:

• a bit line sense amplifier for sensing and amplifying a value in a bit line pair;
• a control unit for controlling the bit line sense amplifier,
• wherein the control unit includes:
• a row control unit for generating a first sense amplifier enabling signal in response to active and precharge command signals;
• a colunm control unit for generating a write colunm selecting signal in response to a read command signal and a write command signal;
• and
• a sense amplifier enabling signal generator for receiving the first sense amplifier enabling signal and the write column selecting signal, thereby to generate a second sense amplifier enabling signal which is inactivated during the predetermined part of the writing operation,
• whereby the bit line sense amplifier is inactivated during a predetermined part of a writing operation prior to activating the column selecting signal corresponding to the write command signal.

A method for driving a semiconductor memory device, comprising:

• generating a first sense amplifier enabling signal in response to active and precharge command signals;
• generating a write column selecting signal in response to read and write command signals;
• generating a second sense amplifier enabling signal, which is inactivated during a predetermined part of an writing operation, in response to the first sense amplifier enabling signal and the write colunm selecting signal;
• and
• sensing/amplifying a value in a bit line pair in response to the second sense amplifier enabling signal.

A method for driving a semiconductor memory device, comprising:

• enabling a bit line sense amplifier in response to an active command signal;
• disabling the bit line sense amplifier during a predetermined part of a writing operation in response to a write command signal;
• enabling the bit line sense amplifier after the predetermined part;
• and
• disabling the bit line sense amplifier in response to a precharge command signal,
• wherein, the bit line sense amplifier is disabled during the predetermined part prior to activating a column selecting signals corresponding to the write command signal.