Memory device and method for precharging a memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsJong-Hoon Jung, Dong-Wook Seo
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Abstract
A memory device having a short precharge time is included. The memory device selects at least two pairs of bit lines and connects the selected two pairs of bit lines to the sense amplifier within a preparatory period during which the two pairs of bit lines and an input to the sense amplifier are precharged. In the preparatory period an input unit of the sense amplifier is precharged through by a plurality of precharge units through more than two bit lines, and thus the precharge time may be decreased. The memory device selects one pair of bit lines and connects the selected pair of bit lines to a sense amplifier within a read/write (data transmission) period.
Claims18
An apparatus for delivering a signal, comprising:
- 2N signal lines;
- N precharge units configured to precharge the 2N signal lines;
- a sense amplifier configured to sense and amplify voltage levels of the signal lines;
- and
- a multiplexer configured to select two of the signal tines among the N signal lines and to connect the selected two signal lines to the sense amplifier within a transmission period;
- wherein the multiplexer is adapted to select at least four of the signal lines among the 2N signal lines and to connect the selected at least four signal lines to the sense amplifier within a preparatory period, and the multiplexer includes N switching units each switching unit being connected to two of the 2N signal lines, the apparatus further comprising:
- a multiplexer control unit configured to receive a multiplexer control signal and to generate N switching signals for controlling the N switching units, wherein at least two of the switching signals are generated based on logically combining a column address signal and the multiplexer control signal, the multiplexer control signal being activated within the preparatory period.
A memory device, comprising:
- 2N bit lines connected to memory cells;
- N precharge units configured to precharge the 2N bit lines;
- a sense amplifier configured to sense and amplify voltage levels of the bit lines;
- and
- a multiplexer configured to select two bit lines among the 2N bit lines and to connect the selected two bit lines to the sense amplifier within a transmission period;
- wherein the multiplexer is adapted to select at least four of bit lines among the 2N bit lines and to connect the selected at least four bit lines to the sense amplifier within a preparatory period,
- and the multiplexer includes N switching units each switching unit being connected to two of the 2N bit lines, the memory device further comprising:
- a multiplexer control unit configured to receive a multiplexer control signal and to generate N switching signals for controlling the N switching units, wherein at least two of the switching signals are generated based on logically combining a column address signal and the multiplexer control signal, the multiplexer control signal being activated withing the preparatory period.
A method for operating a memory device, the memory device including 2N bit lines connected to memory cells, N precharge units configured to precharge the 2N bit lines, a sense amplifier, and a multiplexer configured to selectively connect the sense amplifier with the 2N bit lines, the method comprising:
- selecting more than two bit lines among the 2N bit lines and connecting the selected more than two bit lines to the sense amplifier within a preparatory period and precharging the more than two bit Lines while they are connected to the sense amplifier within the preparatory period;
- selecting two bit lines among the 2N bit lines and connecting the selected two bit lines to the sense amplifier within a data transmission period;
- generating a multiplexer control signal based on an internal clock;
- generating switching signals, based on a column address and the multiplexer control signal, for selecting the more than two bit lines precharged within the preparatory period;
- and then
- generating switching signals, based on the column address signal and the multiplexer control signal, for selecting the two bit lines selected within the transmission period.
Dependencies are inferred from the claim text.