Memory correction system and method
AssigneeHewlett-Packard Development Company, L.P.
InventorLarry Jay Thayer
Life of this patent
Estimating the term…
Abstract
An error correction system and method operable to identify and correct a memory module disposed within a computer memory system. In one embodiment, the memory system comprises a first memory module and a second memory module, each comprising a plurality of memory devices; and a memory controller operably coupled to the first memory module and the second memory module, the memory controller operable to use an error correction code (ECC) word, comprising data and redundant data, to detect module-level errors in the first and second memory modules.
Claims20
A memory system, comprising:
- a first memory module and a second memory module, each comprising a plurality of memory devices;
- and
- a memory controller operably coupled to said first memory module and said second memory module, said memory controller operable to use an error correction code (ECC) word, comprising data and redundant data, to detect module-level errors in said first and second memory modules.
A memory correction method operable with a memory system comprising first and second memory modules organized as an error correction code (ECC) domain, said ECC domain including a redundant memory module, each memory module having a plurality of memory devices, the method comprising:
- reading an ECC word that comprises data and redundant data from said first and second memory modules;
- and
- determining, based on said ECC word, whether one of said first and second memory modules is faulty.
A computer system, comprising:
- a processor complex operably coupled to a memory controller complex, said memory controller complex controlling memory operations with respect to first and second memory modules that are organized as an error correction code (ECC) domain, said first and second memory modules each comprising a plurality of memory devices;
- and
- a module error correction engine operable with said memory controller complex, said module error correction engine operating to determine whether one of said first and second memory modules is defective.
Dependencies are inferred from the claim text.