Semiconductor memory devices having signal delay controller and methods performed therein

A semiconductor memory device including at least one memory cell array with respective memory cells disposed at intersections of rows and columns, the device comprising:

• at least one decoder configured to select at least one of a row and a column for at least one memory cell;
• and
• at least one signal delay controller for equalizing access times for accessing memory cells regardless of a position of the memory cells within the memory cell array in response to a block control signal based on at least one of a position of the at least one memory cell associated with the selected at least of one of row and column and a line loading capacitance value of the selected memory cell, wherein
• the access times are equalized according to a method including,
• providing a decoding signal to a selected memory cell array through a first path without delay when the decoding signal is a signal for accessing a memory cell within a first cell array block having a path length from the decoder longer than a path length for accessing memory cells within a second cell array block, and
• providing the decoding signal to the memory cell array through a second path with delay when the decoding signal is a signal for accessing a memory cell within the second cell array block.

A semiconductor memory device including at least one memory cell array, the memory cell array having memory cells disposed at intersections of rows and columns, the device comprising:

• at least one decoder configured to select at least one of at least one row and at least one column associated with at least one memory cell;
• and
• at least one signal delay controller configured to control a delay of an activation signal applied to the at least one of row and column by the at least one decoder based on at least one of a position of the at least one memory cell associated with the selected at least of one of row and column and a line loading capacitance value of the selected memory cell,
• wherein the at least one signal delay controller is between the at least one decoder and the memory cell array and the memory cell array is divided into at least two cell array blocks, wherein
• the at least one signal delay controller is configured to input the activation signal to the memory cell array through a first path without delay when the activation signal is a signal for accessing a memory cell within a first cell array block having a path length from the at least one decoder that is longer than a path length for accessing memory cells within a second cell array block, and wherein
• the at least one signal delay controller is configured to input the activation signal to the memory cell array through a second path with delay when the activation signal is a signal for accessing a memory cell of the second cell array block.