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US 7,599,230 B2Granted
Semiconductor memory apparatus and method of driving the same
AssigneeHynix Semiconductor Inc.
InventorMun-Phil Park
Life of this patent
Estimating the term…
Abstract
A semiconductor memory apparatus includes: a cell region having a plurality of unit cells each of which has a switching MOS transistor for transferring data. A peripheral circuit unit accesses data stored in the unit cell. A threshold voltage control unit controls the threshold voltage of the switching MOS transistor.
Claims38
A semiconductor memory apparatus comprising:
- a cell region having a plurality of unit cells each of which has a transistor for transferring data, the transistor having a threshold voltage;
- a peripheral circuit unit for accessing data stored in the unit cell;
- and
- a threshold voltage control unit coupled with the transistor and that controls the threshold voltage of the transistor, wherein the threshold voltage control unit comprises:
- a bank bulk voltage supply unit configured to generate and supply the bulk voltage to the transistor arranged in the cell region;
- and
- a peripheral circuit bulk voltage supply unit configured to generate and supply a peripheral circuit bulk voltage to a transistor arranged in the peripheral circuit.
4 more elements
A semiconductor memory apparatus comprising:
- a transistor having a bulk and a threshold voltage that forms a unit cell arranged in a cell region;
- a bank bulk voltage supply unit configured to supply a bank bulk voltage to a bulk of the transistor;
- and
- a peripheral circuit bulk voltage supply unit configured to supply a peripheral circuit bulk voltage to a peripheral circuit,
- wherein the bank bulk voltage supply unit temporarily supplies a first bulk voltage as the bank bulk voltage to the transistor when accessing data so as to decrease the threshold voltage of the transistor.
2 more elements
A semiconductor memory apparatus comprising:
- a transistor that forms a unit cell arranged in a cell region;
- a bulk voltage supply unit configured to selectively supply a first bulk voltage or a second bulk voltage to the bulk of the MOS transistor;
- and
- a command control unit configured to control the bulk voltage supply unit,
- wherein the bulk voltage supply unit temporarily supplies the first bulk voltage to the transistor when accessing data so as to decrease the threshold voltage of the transistor, wherein the bulk voltage supply unit comprises:
- a bulk voltage generation unit configured to supply the first or second bulk voltage;
- and
- a bulk voltage level detector configured to detect the level of the first or second bulk voltage and control the bulk voltage generation unit such that the bulk voltage is at a predetermined level.
5 more elements
A semiconductor memory apparatus comprising:
- a transistor that forms a unit cell arranged in a cell region;
- a bulk voltage supply unit configured to supply a first bulk voltage to a bulk of the MOS transistor and having an output terminal;
- a switch circuit unit coupled with the output terminal of the bulk voltage supply unit and configured to switch the output terminal to a second bulk voltage terminal;
- and
- a command control unit configured to controls the switch circuit unit,
- wherein the output terminal of the bulk voltage supply unit is temporarily switched by the switch circuit unit when accessing data so as to decrease the threshold voltage of the transistors, wherein the bulk voltage supply unit comprises:
- a bulk voltage generation unit configured to supply the first bulk voltage;
- and
- a bulk voltage level detector configured to detect the level of the first or second bulk voltage and control the output of the bulk voltage generation unit such that the bulk voltage is at a predetermined level.
6 more elements
Dependencies are inferred from the claim text.