Semiconductor memory device using pipelined-buffer programming and related method

A semiconductor memory device comprising:

• a cell array having a plurality of memory cells;
• a column select unit capable of selecting bit lines of the cell array in response to a column address;
• a write driver circuit divided into a plurality of write units, each write unit programming memory cells with N-bit data during a programming cycle, wherein N is a positive integer;
• and
• a sense amplifier circuit divided by a plurality of read units, each of which senses memory cells with N-bit data during a program verify operation;
• a selection circuit responsive to a column address, selecting one among the write units during a programming operation and one among the read units during a program verify operation;
• and
• a data input circuit supplying N bits of program data to the selected write unit during a program operation and receiving N bits of verify data from the selected read unit during the program verify operation,
• wherein the data input circuit comprises:
• a write buffer for storing program data bits, the write buffer having a data size larger than N-bit data;
• a bit scanning unit for searching valid program bits among N-bit data received from the write buffer;
• and
• a write driver latch for latching the scanned valid program data bits.