Phase change memory comprising a low-voltage column decoder

A method for applying to memory cells a first voltage and a second voltage, through a memory cell selection circuit having memory cell selection blocks each having selection transistors, the method comprising:

• providing in each memory cell selection block a first selection sub-block and a second selection sub-block in parallel, the first sub-block only having transistors of a first type of conductivity, and the second sub-block only having transistors of a second type of conductivity;
• applying the first voltage to the memory cells through the transistors of the first sub-blocks of the memory cell selection blocks and through one or more additional transistors in series with the transistors of the first sub-blocks and of same type of conductivity as the transistors of the first sub-block;
• and
• applying the second voltage to the memory cells through the transistors of the second sub-blocks of the memory cell selection blocks and through one or more additional transistors in series with the transistors of the second sub-block and of same type of conductivity as the transistors of the second sub-block.

A system, comprising:

• a memory having memory cells;
• a memory cell selection circuit coupled to said memory cells and having memory cell selection blocks each including selection transistors;
• a first device coupled to said memory cell selection circuit to supply a first voltage to said memory cells;
• a second device coupled to said memory cell selection circuit to supply a second voltage to said memory cells;
• wherein:
• each selection block to select a memory cell includes a first selection sub-block to link the memory cell to the first device and a second selection sub-block to link the memory cell to the second device;
• the first sub-block only includes said selection transistors of a first type of conductivity;
• the second sub-block only includes said selection transistors of a second type of conductivity different from the first type of conductivity;
• each memory cell is linked to the first device by a path having the selection transistors of the first sub-block and at least one transistor coupled to the selection transistors of the first sub-block, and is linked to the second device by a path having the selection transistors of the second sub-block and at least one additional transistor coupled to the selection transistors of the second sub-block;
• and
• the at least one transistor coupled to the selection transistors of the first sub-block is of same type of conductivity as the selection transistors of the first sub-block, and the at least one transistor coupled to the selection transistors of the second sub-block is of same type of conductivity as the selection transistors of the second sub-block.

An integrated circuit having a non-volatile memory, the integrated circuit comprising:

• memory cells;
• a memory cell selection circuit having memory cell selection blocks each including selection transistors;
• a first device to supply a first voltage applicable to said memory cells;
• a second device to supply a second voltage applicable to said memory cells;
• wherein:
• each selection block to select a memory cell includes in parallel a first selection sub-block to link the memory cell to the first device and a second selection sub-block to link the memory cell to the second device;
• the first sub-block only includes transistors of a first type of conductivity;
• the second sub-block only includes transistors of a second type of conductivity;
• and
• the first and the second sub-blocks of the one or more selection blocks each comprise at least two transistors in series.

A method for applying to memory cells a first voltage and a second voltage, through a memory cell selection circuit having memory cell selection blocks each having selection transistors, the method comprising:

• providing in each memory cell selection block a first selection sub-block and a second selection sub-block in parallel, the first sub-block only having transistors of a first type of conductivity, and the second sub-block only having transistors of a second type of conductivity;
• applying the first voltage to the memory cells through the first sub-blocks of the one or more selection blocks;
• applying the second voltage to the memory cells through the second sub-blocks of the one or more selection blocks;
• and
• providing at least two transistors in series in the first and the second sub-blocks of the one or more selection blocks.